NXP Semiconductors KE1xF Series, Reference Manual, Page: 1129 / 1483

LPITx_MSR field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
TIF3
Channel 3 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
2
TIF2
Channel 2 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
1
TIF1
Channel 1 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
0
TIF0
Channel 0 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
42.4.5 Module Interrupt Enable Register (LPITx_MIER)
Address: 4003_7000h base + 10h offset = 4003_7010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIE3 TIE2 TIE1 TIE0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 42 Low-power Periodic Interrupt Timer (LPIT)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1129