NXP Semiconductors KE1xF Series, Reference Manual, Page: 108 / 1483

MCM_LMFDLR field descriptions (continued)
Field Description
6.3 Functional description
This section describes the functional description of MCM module.
6.3.1 Interrupts
The MCM's interrupt is generated if any of the following is true:
• FPU input denormal interrupt is enabled (FIDCE) and an input is denormalized
(FIDC)
• FPU inexact interrupt is enabled (FIXCE) and a number is inexact (FIXC)
• FPU underflow interrupt is enabled (FUFCE) and an underflow occurs (FUFC)
• FPU overflow interrupt is enabled (FOFCE) and an overflow occurs (FOFC)
• FPU divide-by-zero interrupt is enabled (FDZCE) and a divide-by-zero occurs
(FDZC)
• FPU invalid operation interrupt is enabled (FIOCE) and an invalid occurs (FIOC)
• SRAM_L correctable(1-bit) ECC error
• SRAM_L uncorrectable ECC error
• SRAM_U correctable (1-bit) ECC error
• SRAM_U uncorrectable ECC error
• PC data parity error
• PC tag parity error
• Cache write buffer error
6.3.1.1 Determining source of the interrupt
To determine the exact source of the interrupt qualify the interrupt status flags with the
corresponding interrupt enable bits.
1. From MCM_ISCR[31:16] && MCM_ISCR[15:0]
2. Search the result for asserted flags, which indicate the exact interrupt sources
NOTE
ECC and Parity interrupts are determined by LMEPECR
(interrupt enable) and LMPEIR (interrupt source).
Functional description
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
108 NXP Semiconductors