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41.5.12.5 CNTIN register synchronization

The CNTIN register synchronization updates the CNTIN register with its buffer value.

This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC =
1). The CNTIN register synchronization can be done only by the enhanced PWM
synchronization (SYNCMODE = 1). The synchronization mechanism is the same as the
MOD register synchronization done by the enhanced PWM synchronization; see

register synchronization

.

41.5.12.6 C(n)V and C(n+1)V register synchronization

The C(n)V and C(n+1)V registers synchronization updates the C(n)V and C(n+1)V
registers with their buffer values.

This synchronization is enabled if (FTMEN = 1) and (SYNCEN = 1). The
synchronization mechanism is the same as the

MOD register synchronization

. However,

it is expected that the C(n)V and C(n+1)V registers be synchronized only by the
enhanced PWM synchronization (SYNCMODE = 1).

41.5.12.7 OUTMASK register synchronization

The OUTMASK register synchronization updates the OUTMASK register with its buffer
value.

The OUTMASK register can be updated at each rising edge of FTM input clock
(SYNCHOM = 0), by the enhanced PWM synchronization (SYNCHOM = 1 and
SYNCMODE = 1) or by the legacy PWM synchronization (SYNCHOM = 1 and
SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized
only by the enhanced PWM synchronization.

In the case of enhanced PWM synchronization, the OUTMASK register synchronization
depends on SWOM and HWOM bits. See the following flowchart:

Chapter 41 FlexTimer Module (FTM)

Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019

NXP Semiconductors

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Summary of Contents for KE1xF Series

Page 1: ...Kinetis KE1xF Sub Family Reference Manual Supports MKE1xF512VLL16 MKE1xF512VLH16 MKE1xF256VLL16 MKE1xF256VLH16 Document Number KE1xFP100M168SF0RM Rev 4 06 2019...

Page 2: ...Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 2 NXP Semiconductors...

Page 3: ...5 Conventions 51 1 5 1 Numbering systems 51 1 5 2 Typographic notation 51 1 5 3 Special terms 52 Chapter 2 Introduction 2 1 Overview 53 2 2 Block Diagram 53 2 3 Module Functional Categories 54 Chapte...

Page 4: ...gister SIM_PLATCGC 77 5 2 7 Flash Configuration Register 1 SIM_FCFG1 78 5 2 8 Flash Configuration Register 2 SIM_FCFG2 81 5 2 9 Unique Identification Register High SIM_UIDH 82 5 2 10 Unique Identifica...

Page 5: ...ister MCM_LMPEIR 104 6 2 13 LMEM Fault Address Register MCM_LMFAR 105 6 2 14 LMEM Fault Attribute Register MCM_LMFATR 106 6 2 15 LMEM Fault Data High Register MCM_LMFDHR 107 6 2 16 LMEM Fault Data Low...

Page 6: ...ord 2 MPU_RGDn_WORD2 124 8 4 7 Region Descriptor n Word 3 MPU_RGDn_WORD3 127 8 4 8 Region Descriptor Alternate Access Control n MPU_RGDAACn 128 8 5 Functional description 130 8 5 1 Access evaluation m...

Page 7: ...ific information for this module 157 10 1 1 Module Interconnectivity 157 10 2 Introduction 162 10 2 1 Features 162 10 3 Functional description 162 10 4 Memory map and register definition 162 10 4 1 TR...

Page 8: ...ation 219 11 6 1 Reset 219 11 6 2 Enabling and configuring sources 219 Chapter 12 Enhanced Direct Memory Access eDMA 12 1 Introduction 223 12 1 1 eDMA system block diagram 223 12 1 2 Block parts 224 1...

Page 9: ...DMA_TCDn_SOFF 267 12 3 24 TCD Transfer Attributes DMA_TCDn_ATTR 268 12 3 25 TCD Minor Byte Count Minor Loop Mapping Disabled DMA_TCDn_NBYTES_MLNO 269 12 3 26 TCD Signed Minor Loop Offset Minor Loop M...

Page 10: ...rogramming errors 293 12 5 3 Arbitration mode considerations 294 12 5 4 Performing DMA transfers 294 12 5 5 Monitoring transfer descriptor status 298 12 5 6 Channel Linking 300 12 5 7 Dynamic programm...

Page 11: ...14 3 1 Cache control register LMEM_PCCCR 325 14 3 2 Cache line control register LMEM_PCCLCR 326 14 3 3 Cache search address register LMEM_PCCSAR 329 14 3 4 Cache read write value register LMEM_PCCCVR...

Page 12: ...Processor 0 Configuration Register MSCM_CP0CFGn 352 15 3 12 On Chip Memory Descriptor Register MSCM_OCMDRn 353 Chapter 16 Flash Acceleration Unit FAU 16 1 Flash Acceleration Unit FAU 357 16 1 1 Intro...

Page 13: ...e RWW 398 17 5 8 Flash Program and Erase 398 17 5 9 FTFE Command Operations 398 17 5 10 Margin Read Commands 405 17 5 11 Flash command descriptions 406 17 5 12 Security 431 17 6 Reset Sequence 433 17...

Page 14: ...emory Map Register Definition 450 19 3 1 Version ID Register SCG_VERID 451 19 3 2 Parameter Register SCG_PARAM 451 19 3 3 Clock Status Register SCG_CSR 452 19 3 4 Run Clock Control Register SCG_RCCR 4...

Page 15: ...19 4 1 SCG Clock Mode Transitions 481 Chapter 20 RTC Oscillator OSC32 20 1 Introduction 485 20 1 1 Features and Modes 485 20 1 2 Block Diagram 485 20 2 RTC Signal Descriptions 486 20 2 1 EXTAL32 Osci...

Page 16: ...558 22 3 1 Boot options 558 22 3 2 Boot sequence 560 Chapter 23 Kinetis ROM Bootloader 23 1 Chip specific information for this module 563 23 1 1 Boot ROM Configuration 563 23 2 Introduction 564 23 3...

Page 17: ...ommand Properties 625 23 6 1 Property Definitions 627 23 7 Verifying the application in flash using CRC 32 628 23 8 Kinetis Bootloader Status Error Codes 629 Chapter 24 Reset Control Module RCM 24 1 C...

Page 18: ...low power modes 656 25 5 1 Peripheral doze 659 25 6 Low power wake up sources 660 25 7 Power supply supervisor 660 Chapter 26 System Mode Controller SMC 26 1 Chip specific information for this module...

Page 19: ...e FPM 684 27 4 2 Low Power Mode LPM 684 27 5 Low Voltage Detect LVD System 684 27 5 1 Low Voltage Reset LVR Operation 685 27 5 2 LVD Interrupt Operation 685 27 5 3 Low voltage warning LVW interrupt op...

Page 20: ...Diagram 697 29 2 EWM Signal Descriptions 698 29 3 Memory Map Register Definition 698 29 3 1 Control Register EWM_CTRL 698 29 3 2 Service Register EWM_SERV 699 29 3 3 Compare Low Register EWM_CMPL 699...

Page 21: ...r WDOG_CS 710 30 3 2 Watchdog Counter Register WDOG_CNT 713 30 3 3 Watchdog Timeout Value Register WDOG_TOVAL 713 30 3 4 Watchdog Window Register WDOG_WIN 714 30 4 Functional description 715 30 4 1 Cl...

Page 22: ...3 1 CRC initialization reinitialization 729 31 3 2 CRC calculations 730 31 3 3 Transpose feature 731 31 3 4 CRC result complement 733 31 4 Usage Guide 733 31 4 1 32 bit POSIX CRC 734 31 4 2 16 bit KER...

Page 23: ...roduction 751 33 1 1 Block diagram 751 33 1 2 Features 752 33 1 3 Modes of operation 752 33 2 External signal description 753 33 2 1 TCK Test clock input 753 33 2 2 TDI Test data input 754 33 2 3 TDO...

Page 24: ...t diagram 770 34 3 Module Signal Description Tables 772 34 3 1 Core Modules 772 34 3 2 System Modules 773 34 3 3 Clock Modules 774 34 3 4 Analog 774 34 3 5 Timer Modules 775 34 3 6 Communication Inter...

Page 25: ...ister PORTx_DFWR 793 35 7 Functional description 794 35 7 1 Pin control 794 35 7 2 Global pin control 795 35 7 3 External interrupts 795 35 7 4 Digital filter 796 Chapter 36 General Purpose Input Outp...

Page 26: ...es 820 37 2 2 Block diagram 821 37 3 ADC signal descriptions 822 37 3 1 Analog Power VDDA 823 37 3 2 Analog Ground VSSA 823 37 3 3 Voltage Reference Select 823 37 3 4 Analog Channel Inputs ADx 824 37...

Page 27: ...9 ADCx_CLP9 845 37 4 22 ADC General Calibration Offset Value Register S ADCx_CLPS_OFS 846 37 4 23 ADC Plus Side General Calibration Offset Value Register 3 ADCx_CLP3_OFS 846 37 4 24 ADC Plus Side Gene...

Page 28: ...fic information for this module 867 38 1 1 Instantiation information 867 38 1 2 CMP Clocking Information 868 38 1 3 Inter connectivity Information 868 38 1 4 Application related Information 869 38 2 I...

Page 29: ...alization 895 38 9 2 Low pass filter 896 38 10 Interrupts 898 38 11 DMA support 898 38 12 DAC functional description 899 38 12 1 Digital to analog converter block diagram 899 38 12 2 DAC resets 899 38...

Page 30: ...918 39 7 Usage Guide 919 39 7 1 12 bit DAC Output 919 39 7 2 12 bit DAC Reference 919 39 7 3 12 bit DAC FIFO 920 Chapter 40 Programmable Delay Block PDB 40 1 Chip specific information for this module...

Page 31: ...el n Delay 4 register PDBx_CHnDLY4 942 40 4 12 Channel n Delay 5 register PDBx_CHnDLY5 942 40 4 13 Channel n Delay 6 register PDBx_CHnDLY6 943 40 4 14 Channel n Delay 7 register PDBx_CHnDLY7 944 40 4...

Page 32: ...63 41 2 4 Block Diagram 963 41 3 FTM signal descriptions 965 41 4 Memory map and register definition 965 41 4 1 Memory map 965 41 4 2 Register descriptions 966 41 4 3 Status And Control FTMx_SC 973 41...

Page 33: ...2 41 4 25 FTM Inverting Control FTMx_INVCTRL 1014 41 4 26 FTM Software Output Control FTMx_SWOCTRL 1015 41 4 27 FTM PWM Load FTMx_PWMLOAD 1018 41 4 28 Half Cycle Register FTMx_HCR 1020 41 4 29 Mirror...

Page 34: ...rigger 1080 41 5 24 Capture Test Mode 1083 41 5 25 DMA 1084 41 5 26 Dual Edge Capture mode 1085 41 5 27 Quadrature Decoder mode 1092 41 5 28 Debug mode 1097 41 5 29 Reload Points 1098 41 5 30 Global L...

Page 35: ...Overview 1123 42 2 2 Block Diagram 1124 42 3 Modes of operation 1125 42 4 Memory Map and Registers 1125 42 4 1 Version ID Register LPITx_VERID 1126 42 4 2 Parameter Register LPITx_PARAM 1127 42 4 3 M...

Page 36: ...43 3 2 PWTIN 3 0 pulse width timer capture inputs 1148 43 3 3 ALTCLK alternative clock source for counter 1148 43 4 Memory Map and Register Descriptions 1148 43 4 1 Pulse Width Timer Control and Stat...

Page 37: ...tion for this module 1165 44 1 1 Instantiation Information 1165 44 1 2 LPTMR Clocking Information 1165 44 1 3 Inter connectivity Information 1166 44 2 Introduction 1167 44 2 1 Features 1167 44 2 2 Mod...

Page 38: ...er connectivity Information 1180 45 2 Introduction 1181 45 2 1 Features 1181 45 2 2 Modes of operation 1182 45 2 3 RTC signal descriptions 1182 45 3 Register definition 1182 45 3 1 RTC Time Seconds Re...

Page 39: ...200 Chapter 46 Low Power Serial Peripheral Interface LPSPI 46 1 Chip specific information for this module 1201 46 1 1 Instantiation Information 1201 46 1 2 Module Clocking Information for LPUART LPSPI...

Page 40: ...it Command Register LPSPIx_TCR 1220 46 3 15 Transmit Data Register LPSPIx_TDR 1223 46 3 16 Receive Status Register LPSPIx_RSR 1224 46 3 17 Receive Data Register LPSPIx_RDR 1225 46 4 Functional descrip...

Page 41: ...ter 3 LPI2Cx_MCFGR3 1254 47 3 11 Master Data Match Register LPI2Cx_MDMR 1254 47 3 12 Master Clock Configuration Register 0 LPI2Cx_MCCR0 1255 47 3 13 Master Clock Configuration Register 1 LPI2Cx_MCCR1...

Page 42: ...mitter LPUART 48 1 Chip specific information for this module 1287 48 1 1 Instantiation Information 1287 48 1 2 Module Clocking Information for LPUART LPSPI LPI2C FlexIO and LPIT 1287 48 1 3 Inter conn...

Page 43: ...er Register FLEXIO_PARAM 1341 49 3 3 FlexIO Control Register FLEXIO_CTRL 1341 49 3 4 Pin State Register FLEXIO_PIN 1342 49 3 5 Shifter Status Register FLEXIO_SHIFTSTAT 1343 49 3 6 Shifter Error Regist...

Page 44: ...n 1357 49 4 2 Timer operation 1359 49 4 3 Pin operation 1361 49 5 Application Information 1362 49 5 1 UART Transmit 1362 49 5 2 UART Receive 1363 49 5 3 SPI Master 1365 49 5 4 SPI Slave 1367 49 5 5 I2...

Page 45: ...1406 50 4 10 Interrupt Masks 1 register CANx_IMASK1 1412 50 4 11 Interrupt Flags 1 register CANx_IFLAG1 1412 50 4 12 Control 2 register CANx_CTRL2 1415 50 4 13 Error and Status 2 register CANx_ESR2 14...

Page 46: ...10 Modes of operation details 1462 50 5 11 Interrupts 1466 50 5 12 Bus interface 1467 50 6 Initialization application information 1468 50 6 1 FlexCAN initialization sequence 1468 50 7 Usage Guide 1470...

Page 47: ...chip 2 Chapters in the second set are organized into functional groupings that detail particular areas of functionality Examples of these groupings are clocking timers and communication interfaces Eac...

Page 48: ...rences Thetabledoesnot list feature detailsthat theinstancesshare Table 49 1 eSCI instance feature differences Instance DMA support eSCI_A and eSCI_B Yes eSCI_C eSCI_D eSCI_E and eSCI_F No description...

Page 49: ...CR SWT_TO SWT_WN and SWT_SK registersareread only TheSWT memory map isshown in thefollowing table SWT memory map Address offset hex Register name Width in bits Access Reset value Section page 0 SWT Co...

Page 50: ...Nexus_3_0 arbitrates with Core0 data for XBAR port 1 Core1 instruction 2 1 Core1 data 3 1 Nexus_3_1 9 Nexus_3_1 arbitrates with Core1 data for XBAR port 3 Table continues on the next page Sample Refer...

Page 51: ...l numbers are followed by this suffix only when the possibility of confusion exists In general decimal numbers are shown without a suffix h Hexadecimal number For example the hexadecimal equivalent of...

Page 52: ...ial meanings Term Meaning asserted Refers to the state of a signal as follows An active high signal is asserted when high 1 An active low signal is asserted when low 0 deasserted Refers to the state o...

Page 53: ...es of ARM Cortex M4 MCUs and product family It also presents high level descriptions of the modules available on the device covered by this document 2 2 Block Diagram The following figure shows a top...

Page 54: ...O High drive Digital filters I O 8 pins OSC32 upto 89 all ports OSC FIRC SIRC PLL WDOG PMC ECC FAC EWM Kinetis KE1xF Sub Family FPU x2 LPI C 2 FlexTimer 8ch x4 FlexCAN upto x2 PWT FlexIO TRGMUX 12 bit...

Page 55: ...er Oscillator LPO Peripheral Clock Control PCC Security and integrity modules Cyclic Redundancy Check CRC module for error detection Error correcting code ECC on Flash and SRAM memories Flash Access C...

Page 56: ...egory Description High drive I O pins see Pin properties Digital filters see Ports summary table in Port control and interrupt module features Module Functional Categories Kinetis KE1xF Sub Family Ref...

Page 57: ...ogy ensuring high code density and reduced program memory requirements The Cortex M4 instruction set provides the exceptional performance expected of a modern 32 bit architecture with the high code de...

Page 58: ...ce for trace The following interfaces are implemented on the Cortex M4 processor of this device I Code D Code and System bus PPB bus NVIC interface Trace port interface Debug port interface INTNMI INT...

Page 59: ...nfiguration The System Tick Timer s clock source is always the core clock CORE_CLK on this device This results in the following The CLKSOURCE bit in SysTick Control and Status Register SYST_CSR is alw...

Page 60: ...SysTick Clock Configuration Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 60 NXP Semiconductors...

Page 61: ...Interrupt NMI The NVIC registers are located within the processor s internal System Control Space SCS with base address of 0xE000E000 Most of the NVIC registers are accessible only in privileged mode...

Page 62: ...source assignments are defined in the following table Vector number the value stored on the stack when an interrupt is serviced IRQ number non core interrupt source count which is the vector number mi...

Page 63: ...lete 0x0000_0060 24 8 0 2 DMA DMA channel 8 transfer complete 0x0000_0064 25 9 0 2 DMA DMA channel 9 transfer complete 0x0000_0068 26 10 0 2 DMA DMA channel 10 transfer complete 0x0000_006C 27 11 0 2...

Page 64: ...00E4 57 41 1 10 CMP1 0x0000_00E8 58 42 1 10 FTM0 Single interrupt vector for all sources 0x0000_00EC 59 43 1 10 FTM1 Single interrupt vector for all sources 0x0000_00F0 60 44 1 11 FTM2 Single interrup...

Page 65: ...ror 0x0000_0180 96 80 2 20 CAN0 Wake Up 0x0000_0184 97 81 2 20 CAN0 OR ed Message buffer 0x0000_0188 98 82 2 20 CAN0 Reserved 0x0000_018C 99 83 2 20 CAN0 Reserved MB extension 32 47 0x0000_0190 100 84...

Page 66: ...div 32 3 Indicates the NVIC s IPR register number used for this IRQ The equation to calculate this value is IRQ div 4 The NVIC registers you would use to configure the interrupt are NVIC_ISER1 NVIC_I...

Page 67: ...selection Flash configuration System device unique identification UID 5 2 Memory map and register definition NOTE The SIM registers can only be written in the supervisor mode In the user mode write a...

Page 68: ...R See section 5 2 10 82 4004_805C Unique Identification Register Mid Low SIM_UIDML 32 R See section 5 2 11 83 4004_8060 Unique Identification Register Low SIM_UIDL 32 R See section 5 2 12 83 4004_806...

Page 69: ...B2 channel 0 back to back operation with ADC2 COCO 7 0 1 Channel 0 of PDB0 PDB1 and PDB2 back to back operation with COCO 7 0 of ADC0 ADC1 and ADC2 12 TRACECLK_SEL Debug trace clock select Selects cor...

Page 70: ...Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FTM3FLTxSEL 0 FTM2FLTxSEL 0 FTM1FLTxSEL 0 FTM0FLTxSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_FTMOPT0 field descriptions Field Description 31 30 FTM3C...

Page 71: ...in 01 FTM0 external clock driven by TCLK1 pin 10 FTM0 external clock driven by TCLK2 pin 11 No clock input 23 15 Reserved This field is reserved This read only field is reserved and always has the val...

Page 72: ...X Select Selects the source of FTM0 fault Every bit means one fault input respectively NOTE The pin source for fault must be configured for the FTM module fault function through the appropriate pin co...

Page 73: ...will have up to 8 pre triggers for this ADC2 channel control 0 PDB output 1 TRGMUX output 15 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 12 ADC1P...

Page 74: ...01 software pre trigger 1 110 software pre trigger 2 111 software pre trigger 3 0 ADC0TRGSEL ADC0 trigger source select Selects trigger source for ADC0 0 PDB output 1 TRGMUX output 5 2 4 FTM Option Re...

Page 75: ...M2CH0SEL FTM2 CH0 Select Selects FTM2 CH0 input 00 FTM2_CH0 input 01 CMP0 output 10 CMP1 output 11 CMP2 output 5 4 FTM1CH0SEL FTM1 CH0 Select Selects FTM1 CH0 input 00 FTM1_CH0 input 01 CMP0 output 10...

Page 76: ...004_8000h base 24h offset 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FAMILYID SUBFAMID SERIESID RAMSIZE REVID PROJECTID PINID W Reset x x x...

Page 77: ...f the device 0000111 64 pin 0001010 100 pin 5 2 6 Platform Clock Gating Control Register SIM_PLATCGC Address 4004_8000h base 40h offset 4004_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R...

Page 78: ...Control Controls the clock gating to the MSCM module 0 Clock disabled 1 Clock enabled 5 2 7 Flash Configuration Register 1 SIM_FCFG1 NOTE Reset value of NVMSIZE PFSIZE EEERAM_SIZE DEPART loaded during...

Page 79: ...lash memory 0 25 KB protection region 0001 16 KB of program flash memory 0 5 KB protection region 0011 32 KB of program flash memory 1 KB protection region 0101 64 KB of program flash memory 2 KB prot...

Page 80: ...is bit should be clear during VLP modes The Flash will be automatically enabled again at the end of Wait mode so interrupt vectors do not need to be relocated out of Flash memory The wakeup time from...

Page 81: ...s has the value 0 30 24 MAXADDR0 Max address block 0 This field concatenated with 13 trailing zeros indicates the first invalid address of program flash block 0 For example if MAXADDR0 0x10 the first...

Page 82: ...ion Unique identification for the device 5 2 10 Unique Identification Register Mid High SIM_UIDMH Address 4004_8000h base 58h offset 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 83: ...ication Unique identification for the device 5 2 12 Unique Identification Register Low SIM_UIDL Address 4004_8000h base 60h offset 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 84: ...TRACEDIV Trace clock divider divisor NOTE To configure TRACEDIV the user must disable TRACEDIVEN at first and then enable it after setting TRACEDIV This field sets the divide value for the fractional...

Page 85: ..._MISCTRL field descriptions Field Description 31 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 SW_INTERRUPT Software Interrupt 0 Disables software i...

Page 86: ...Memory map and register definition Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 86 NXP Semiconductors...

Page 87: ...riptions below describe the registers using byte addresses MCM memory map Absolute address hex Register name Width in bits Access Reset value Section page E008_0008 Crossbar Switch AXBS Slave Configur...

Page 88: ...000_0000h 6 2 13 105 E008_0494 LMEM Fault Attribute Register MCM_LMFATR 32 R W 0000_0000h 6 2 14 106 E008_04A0 LMEM Fault Data High Register MCM_LMFDHR 32 R 0000_0000h 6 2 15 107 E008_04A4 LMEM Fault...

Page 89: ...MC field indicates whether there is a corresponding connection to the AXBS master input port 0 A bus master connection to AXBS input port n is absent 1 A bus master connection to AXBS input port n is...

Page 90: ...served This field is reserved This read only field is reserved and always has the value 0 26 SRAMUWP SRAM_U write protect When this bit is set writes to SRAM_U array generates a bus error 25 24 SRAMUA...

Page 91: ...based on the processor s FPSCR register Attempted writes to these bits are ignored Once set the flags remain asserted until software clears the corresponding FPSCR bit Address E008_0000h base 10h off...

Page 92: ...or termination reported on a system bus transfer initiated from the cache s write buffer 0 Disable error interrupt 1 Enable error interrupt 19 16 Reserved This field is reserved This read only field i...

Page 93: ...CR DZC bit 0 No interrupt 1 Interrupt occurred 8 FIOC FPU invalid operation interrupt status This read only bit is a copy of the core s FPSCR IOC bit and signals an illegal operation has been detected...

Page 94: ...SCR CWBER Attempted writes have no effect Address E008_0000h base 20h offset E008_0020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ADDRESS W Reset x x...

Page 95: ...inal cache write buffer error termination until the MCM_ISCR CWBER is written with a 1 to clear it and rearm the capture logic This bit is set by the hardware and cleared whenever software writes a 1...

Page 96: ...privilege level Indicates the privilege level of the cache write buffer access when the error was detected 0 User mode 1 Supervisor privileged mode 0 BEDA Bus Error Data Access type Indicates the typ...

Page 97: ...r mode process If the PID of the process does not match the value in this register a bus error occurs See the MPU chapter for more details Address E008_0000h base 30h offset E008_0030h Bit 31 30 29 28...

Page 98: ...ead only field is reserved and always has the value 0 2 CPOWOI Compute Operation wakeup on interrupt 0 No effect 1 When set the CPOREQ is cleared on any interrupt or exception vector fetch 1 CPOACK Co...

Page 99: ...d memories as well as configurable controls where appropriate Privileged 32 bit reads from a processor core or the debugger return the appropriate processor information Reads from any other bus master...

Page 100: ...V Reserved Reserved LMSZH LMSZ WY DPW RO W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MT Reserved Reserved CF1 CF0 W Reset x x x x x x x x x x x x x x x x Notes...

Page 101: ...ld provides an encoded value of the local memory size The capacity of the memory is expressed as Size bytes 2 9 SZ where SZ is non zero a SZ 0 indicates the memory is not present 0000 no LMEMn 0 KB 00...

Page 102: ...al memory 000 SRAM_L 001 SRAM_U 010 PC Cache 011 PS Cache 12 Reserved This field is reserved 11 8 Reserved This field is reserved 7 4 CF1 Control Field 1 for Cache Parity control functions CF1 3 PCPFE...

Page 103: ...orting enabled 0 reporting disabled 19 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 ERPR Enable RAM Parity Reporting 1 reporting enabled 0 reportin...

Page 104: ...d always has the value 0 28 24 PEELOC Parity or ECC Error Location 5 h00 a non correctable ECC event from SRAM_L 5 h01 a non correctable ECC event from SRAM_U 5 h08 a 1 bit correctable ECC event from...

Page 105: ...AR Address E008_0000h base 490h offset E008_0490h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EFADD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 106: ...ield Description 31 OVR Overrun 30 Reserved This field is reserved This read only field is reserved and always has the value 0 29 24 Reserved This field is reserved This read only field is reserved an...

Page 107: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PEFDH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_LMFDHR field descriptions Field Des...

Page 108: ...ro occurs FDZC FPU invalid operation interrupt is enabled FIOCE and an invalid occurs FIOC SRAM_L correctable 1 bit ECC error SRAM_L uncorrectable ECC error SRAM_U correctable 1 bit ECC error SRAM_U u...

Page 109: ...ARM core code bus 0 ARM core system bus 1 DMA 2 7 1 1 2 Crossbar Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows Slave module Slave port number Protected...

Page 110: ...ng arbitration among the bus masters when they access the same slave 7 2 1 Features The crossbar switch includes these features Symmetric crossbar bus switch implementation Allows concurrent accesses...

Page 111: ...ave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access The master can also lose control of the slave port if another higher p...

Page 112: ...vel is higher than that of the master that currently has control over the slave port unless the slave port is in a parked state The slave port performs an arbitration check at every clock edge to ensu...

Page 113: ...the next transfer boundary or possibly on the next clock cycle if the current master has no pending access request As an example of arbitration in round robin mode assume the crossbar is implemented...

Page 114: ...Initialization application information Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 114 NXP Semiconductors...

Page 115: ...0 Flash Controller and boot ROM Crossbar slave port 1 MPU slave port 1 SRAM backdoor Code Bus MPU slave port 2 all code bus address 0x0000_0000 to 0x1FFF_FFFF System Bus MPU slave port 3 all system b...

Page 116: ...e allowed to complete while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response 8 3 1 Block diagram A simplified block d...

Page 117: ...8 program visible 128 bit region descriptors accessible by four 32 bit words each Each region descriptor defines a modulo 32 byte space aligned anywhere in memory Region sizes can vary from 32 bytes...

Page 118: ...er information in this module MPU memory map Absolute address hex Register name Width in bits Access Reset value Section page 4000_D000 Control Error Status Register MPU_CESR 32 R W 0081_4001h 8 4 1 1...

Page 119: ...4 5 124 4000_D448 Region Descriptor n Word 2 MPU_RGD4_WORD2 32 R W See section 8 4 6 124 4000_D44C Region Descriptor n Word 3 MPU_RGD4_WORD3 32 R W See section 8 4 7 127 4000_D450 Region Descriptor n...

Page 120: ...iption 31 28 SPERR Slave Port n Error Indicates a captured error in EARn and EDRn This bit is set when the hardware detects an error and records the faulting address and attributes It is cleared by wr...

Page 121: ...2 Error Address Register slave port n MPU_EARn When the MPU detects an access error on slave port n the 32 bit reference address is captured in this read only register and the corresponding bit in CES...

Page 122: ...ol Detail Indicates the region descriptor with the access error If EDRn contains a captured error and EACD is cleared an access did not hit in any region descriptor If only a single EACD bit is set th...

Page 123: ...base 400h offset 16d i where i 0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SRTADDR 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 124: ...memory region NOTE The MPU does not verify that ENDADDR SRTADDR Reserved This field is reserved 8 4 6 Region Descriptor n Word 2 MPU_RGDn_WORD2 The third word of the region descriptor defines the acc...

Page 125: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes Reset value of RGD0_WORD2 is 0061_F7DFh Reset value of RGD 1 7 _WORD2 is 0000_0000h MPU_RGDn_WORD2 field descriptions Field Description 31 M7RE Bus Master 7 Read Enab...

Page 126: ...bus master 3 in Supervisor mode 00 r w x read write and execute allowed 01 r x read and execute allowed but no write 10 r w read and write allowed but no execute 11 Same as User mode defined in M3UM 2...

Page 127: ...valid bit Address 4000_D000h base 40Ch offset 16d i where i 0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PID PIDMASK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8...

Page 128: ...d 1 Region descriptor is valid 8 4 8 Region Descriptor Alternate Access Control n MPU_RGDAACn Because software may adjust only the access controls within a region descriptor RGDn_WORD2 as different ta...

Page 129: ...terminate with an access error and the read is not performed 1 Bus master 4 reads allowed 24 M4WE Bus Master 4 Write Enable 0 Bus master 4 writes terminate with an access error and the write is not p...

Page 130: ...5 M0PE Bus Master 0 Process Identifier Enable See M3PE description 4 3 M0SM Bus Master 0 Supervisor Mode Access Control See M3SM description M0UM Bus Master 0 User Mode Access Control See M3UM descrip...

Page 131: ...ord0 SRTADDR addr 31 5 RGDn_Word1 ENDADDR RGDn_Word3 VLD where addr is the current reference address RGDn_Word0 SRTADDR and RGDn_Word1 ENDADDR are the start and end addresses and RGDn_Word3 VLD is the...

Page 132: ...tion violation definition Description MxUM Protection violation r w x Instruction fetch read 0 Yes no execute permission 1 No access is allowed Data read 0 Yes no read permission 1 No access is allowe...

Page 133: ...disabled CESR VLD 0 Note A region descriptor must be set to allow access to the MPU registers if further changes are needed 8 7 Application information In an operational system interfacing with the MP...

Page 134: ...ng E A D Rn CESR SPERR signals which error registers contain captured fault data Overlapping region descriptors Applying overlapping regions often reduces the number of descriptors required for a give...

Page 135: ...nd RGD4 defines another shared data space this one for passing data from CP1 to CP0 For this overlapping space CP0 has r r permission while CP1 has rw r rw permission The non overlapped space of RGD4...

Page 136: ...s Register Reset value RGD0_WORD0 0000_0000h RGD0_WORD1 FFFF_FFFFh RGD0_WORD2 0061_F7DFh RGD0_WORD3 0000_0001h RGDAAC0 0061_F7DFh 8 8 3 Write Access Restrictions for RGD0 Registers In addition to conf...

Page 137: ...isters or register fields RGD0_WORD0 RGD0_WORD1 RGD0_WORD3 RGD0_WORD2 M1SM M1UM RGDAAC0 M1SM M1UM NOTE Changes to the RGD0_WORD2 alterable fields should be done via a write to RGDAAC0 Debugger Yes DMA...

Page 138: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 138 NXP Semiconductors...

Page 139: ...ash memory Peripheral Access Control Register Peripheral bridge slot number AIPS_PACRn n AIPS_OPACRn n 32 9 2 Introduction The peripheral bridge converts the crossbar switch interface to an interface...

Page 140: ...o only by a 32 bit aligned access The peripheral bridge registers are mapped into the Peripheral Access Control Register A PACRA PACR0 address space AIPS memory map Absolute address hex Register name...

Page 141: ...0_0068 Off Platform Peripheral Access Control Register AIPS_OPACRK 32 R W See section 9 3 3 149 4000_006C Off Platform Peripheral Access Control Register AIPS_OPACRL 32 R W See section 9 3 3 149 4000_...

Page 142: ...ed for read accesses 29 MTW0 Master 0 Trusted For Writes Determines whether the master is trusted for write accesses 0 This master is not trusted for write accesses 1 This master is trusted for write...

Page 143: ...ed for write accesses 20 MPL2 Master 2 Privilege Level Specifies how the privilege level of the master is determined 0 Accesses from this master are forced to user mode 1 Accesses from this master are...

Page 144: ...8 PACR29 PACR30 PACR31 Address 4000_0000h base 20h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SP0 WP0 TP0 0 SP1 WP1 TP1 0 SP2 WP2 TP2 0 SP3 WP3 TP3 W Reset 0...

Page 145: ...an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses 25 WP...

Page 146: ...an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses 17 W...

Page 147: ...an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses 9 WP...

Page 148: ...pheral requires supervisor privilege level for accesses When this field is set the master privilege level must indicate the supervisor access attribute and the MPRx MPLn control field for the master m...

Page 149: ...CR31 0x50 OPACRE OPACR32 OPACR33 OPACR34 OPACR35 OPACR36 OPACR37 OPACR38 OPACR39 0x54 OPACRF OPACR40 OPACR41 OPACR42 OPACR43 OPACR44 OPACR45 OPACR46 OPACR47 0x58 OPACRG OPACR48 OPACR49 OPACR50 OPACR51...

Page 150: ...1 Accesses from an untrusted master are not allowed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 SP1 Supervisor Protect Determines whether the per...

Page 151: ...1 Accesses from an untrusted master are not allowed 19 Reserved This field is reserved This read only field is reserved and always has the value 0 18 SP3 Supervisor Protect Determines whether the per...

Page 152: ...ed 1 Accesses from an untrusted master are not allowed 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 SP5 Supervisor Protect Determines whether the p...

Page 153: ...master are allowed 1 Accesses from an untrusted master are not allowed 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 SP7 Supervisor Protect Determines...

Page 154: ...inates with an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for ac...

Page 155: ...an access is attempted by an untrusted master the access terminates with an error response and no peripheral access initiates 0 Accesses from an untrusted master are allowed 1 Accesses from an untrus...

Page 156: ...ss than or equal to the designated peripheral slot size If an access is attempted that is larger than the targeted port an error response is generated Functional description Kinetis KE1xF Sub Family R...

Page 157: ...0 TRGMUX0 supports up to 32 input sources and its output will be the target modules With the TRGMUX each peripheral which accepts external triggers will usually have one specific 32 bit trigger contro...

Page 158: ...rnal output etc which needs more than 4 trigger inputs multiple control registers are created to support that The trigger input and peripheral trigger control are assigned as the following figure indi...

Page 159: ...conversion complete trigger for data result A ADCx_COCOB ADCx conversion complete trigger for data result B PDBx_Pulse0 PDBx pulse0 trigger RTC_second RTC second trigger RTC_alarm RTC alarm trigger L...

Page 160: ...ULT0 out50 FTM2_FAULT1 out51 out52 out53 out54 out55 TRGMUX_PDB0 out56 out57 X out58 X out59 X out60 out61 X out62 X out63 X PDB0_TRG_IN TRGMUX0 OR ADC1_ADHWT OR ADC0_ADHWT CMP0_SAMPLE CMP1_SAMPLE Tri...

Page 161: ...UT6 TRGMUX_B_OUT3 TRGMUX_B_OUT4 TRGMUX_B_OUT7 TRGMUX_FLEXIO TRGMUX_LPIT0 TRGMUX_LPUART0 TRGMUX_LPUART1 TRGMUX_LPI2C0 TRGMUX_LPI2C1 TRGMUX_LPSPI0 TRGMUX_LPSPI1 TRGMUX_LPTMR0 Reserved TRGMUX_PWT OUT out...

Page 162: ...3 Functional description The Trigger MUX module allows software to configure the trigger inputs for various peripherals Each peripheral has its own unique TRGMUX register that is used to select the tr...

Page 163: ..._TRIG is selected 000_1100 0x0C FTM1_TRIG is selected 000_1101 0x0D FTM2_TRIG is selected 000_1110 0x0E FTM3_TRIG is selected 000_1111 0x0F ADC0_COCOA is selected 001_0000 0x10 ADC0_COCOB is selected...

Page 164: ...d 011_0100 0x34 Unused 011_0101 0x35 Unused 011_0110 0x36 Unused 011_0111 0x37 Unused 011_1000 0x38 Unused 011_1001 0x39 Unused 011_1010 0x3A Unused 011_1011 0x3B Unused 011_1100 0x3C Unused 011_1101...

Page 165: ...101_1010 0x5A Unused 101_1011 0x5B Unused 101_1100 0x5C Unused 101_1101 0x5D Unused 101_1110 0x5E Unused 101_1111 0x5F Unused 110_0000 0x60 Unused 110_0001 0x61 Unused 110_0010 0x62 Unused 110_0011 0...

Page 166: ...RGMUX_ADC1 32 RW 00000000h 40062014h TRGMUX ADC2 TRGMUX_ADC2 32 RW 00000000h 40062018h TRGMUX DAC0 TRGMUX_DAC0 32 RW 00000000h 4006201Ch TRGMUX CMP0 TRGMUX_CMP0 32 RW 00000000h 40062020h TRGMUX CMP1 T...

Page 167: ...32 RW 00000000h 40062068h TRGMUX Reserved TRGMUX_Reserved 32 RO 00000000h 4006206Ch TRGMUX PWT TRGMUX_PWT 32 RW 00000000h 10 4 1 2 TRGMUX DMAMUX0 TRGMUX_DMAMUX0 10 4 1 2 1 Address Register Offset TRGM...

Page 168: ...n the Features section for bit field information 15 This read only bit field is reserved and always has the value 0 14 8 SEL1 Trigger MUX Input 1 Source Select This read write bit field is used to con...

Page 169: ...gger MUX Input 2 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bit Fields table in the Features section for bit field i...

Page 170: ...elect Bit Fields table in the Features section for bit field information 23 This read only bit field is reserved and always has the value 0 22 16 SEL2 Trigger MUX Input 2 Source Select This read write...

Page 171: ...4 3 2 1 0 R Rese rved SEL1 Rese rved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 4 1 5 3 Fields Field Function 31 LK Enable This bit shows whether the register can be written or not 0b Register c...

Page 172: ...y bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input 0 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 0 Refer to the...

Page 173: ...e in the Features section for bit field information 15 This read only bit field is reserved and always has the value 0 14 8 SEL1 Trigger MUX Input 1 Source Select This read write bit field is used to...

Page 174: ...2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bit Fields table in the Features section for bit fi...

Page 175: ...read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0 15 T...

Page 176: ...shows whether the register can be written or not 0b Register can be written 1b Register cannot be written until the next system Reset 30 24 This read only bit field is reserved and always has the val...

Page 177: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Rese rved Reserved Rese rved SEL0 W Rese...

Page 178: ...o configure the MUX select for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 10 4 1 11 TRGMUX CMP2 TRGMUX_CMP2 10 4 1 11 1 Address R...

Page 179: ...d is reserved and always has the value 0 14 8 This read only bit field is reserved and always has the value 0 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Inp...

Page 180: ...2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bit Fields table in the Features section for bit fi...

Page 181: ...lect Bit Fields table in the Features section for bit field information 23 This read only bit field is reserved and always has the value 0 22 16 SEL2 Trigger MUX Input 2 Source Select This read write...

Page 182: ...5 4 3 2 1 0 R Rese rved SEL1 Rese rved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 4 1 14 3 Fields Field Function 31 LK Enable This bit shows whether the register can be written or not 0b Registe...

Page 183: ...it field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input 0 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 0 Refer to the Sel...

Page 184: ...le in the Features section for bit field information 15 This read only bit field is reserved and always has the value 0 14 8 SEL1 Trigger MUX Input 1 Source Select This read write bit field is used to...

Page 185: ...lue 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0 15 This read only bit field is reserved and always has th...

Page 186: ...is read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0 1...

Page 187: ...shows whether the register can be written or not 0b Register can be written 1b Register cannot be written until the next system Reset 30 24 This read only bit field is reserved and always has the val...

Page 188: ...19 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK SEL3 Rese rved SEL2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Rese rved SEL1 Rese rve...

Page 189: ...ral trigger input 1 Refer to the Select Bit Fields table in the Features section for bit field information 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input...

Page 190: ...the Features section for bit field information 15 This read only bit field is reserved and always has the value 0 14 8 SEL1 Trigger MUX Input 1 Source Select This read write bit field is used to conf...

Page 191: ...0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0 15 This read only bit field is reserved and always has the v...

Page 192: ...his read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0...

Page 193: ...bit shows whether the register can be written or not 0b Register can be written 1b Register cannot be written until the next system Reset 30 24 This read only bit field is reserved and always has the...

Page 194: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Rese rved Reserved Rese rved SEL0 W...

Page 195: ...nfigure the MUX select for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 10 4 1 25 TRGMUX LPSPI0 TRGMUX_LPSPI0 10 4 1 25 1 Address R...

Page 196: ...is reserved and always has the value 0 14 8 This read only bit field is reserved and always has the value 0 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input...

Page 197: ...e 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0 15 This read only bit field is reserved and always has the...

Page 198: ...his read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and always has the value 0...

Page 199: ...This bit shows whether the register can be written or not 0b Register can be written 1b Register cannot be written until the next system Reset 30 24 This read only bit field is reserved and always has...

Page 200: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Rese rved Reserved Rese rved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 4 1 29 3 Fields Field Function 31 LK Enab...

Page 201: ...ds Field Function 5 0 SEL This read write bit field is used to configure the MUX select for the peripheral trigger inputs 000_0000 0x00 Trigger function is disabled 000_0001 0x01 VDD is selected 000_0...

Page 202: ..._1011 0x1B PDB2_DAC is selected 001_1100 0x1C PDB2_Pulse is selected 001_1101 0x1D ADC2_COCOA is selected 001_1110 0x1E ADC2_COCOB is selected 001_1111 0x1F Unused 010_0000 0x20 Unused 010_0001 0x21 U...

Page 203: ...100_0101 0x45 Unused 100_0110 0x46 Unused 100_0111 0x47 Unused 100_1000 0x48 Unused 100_1001 0x49 Unused 100_1010 0x4A Unused 100_1011 0x4B Unused 100_1100 0x4C Unused 100_1101 0x4D Unused 100_1110 0...

Page 204: ...0x6A Unused 110_1011 0x6B Unused 110_1100 0x6C Unused 110_1101 0x6D Unused 110_1110 0x6E Unused 110_1111 0x6F Unused 111_0000 0x70 Unused 111_0001 0x71 Unused 111_0010 0x72 Unused 111_0011 0x73 Unuse...

Page 205: ...R LK SEL3 Rese rved SEL2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Rese rved SEL1 Rese rved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 4 2 2 4 Fields Fi...

Page 206: ...ral trigger input 1 Refer to the Select Bit Fields table in the Features section for bit field information 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input...

Page 207: ...onfigure the MUX select for peripheral trigger input 1 Refer to the Select Bit Fields table in the Features section for bit field information 7 This read only bit field is reserved and always has the...

Page 208: ...C For details please refer to ADC Trigger Concept Use Case section 10 5 2 CMP Window Sample Input PDB and LPIT could be used to generate pulse output which can be used as sampling windows of CMP block...

Page 209: ...sources and a specific DMA channel Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table Asynchronous DMA requests can be...

Page 210: ...Channel 4 25 FTM0 Channel 5 26 FTM0 Channel 6 27 FTM0 Channel 7 28 FTM1 Channel 0 29 FTM1 Channel 1 30 FTM2 Channel 0 31 FTM2 Channel 1 32 LPI2C1 or FTM3 LPI2C1 Receiveor FTM3 Channel 0 Yes for LPI2C1...

Page 211: ...source 0 or any of the reserved sources disables that DMA channel 2 The several FlexCAN DMA Rx will be OR d with the DAC 11 1 1 2 DMA trigger sources The DMAMUX on this device also supports a periodic...

Page 212: ...Source 2 Source 3 Always 1 DMA channel n Always y Source x Trigger 1 Trigger z DMA channel 1 DMAMUX Figure 11 1 DMAMUX block diagram 11 2 2 Features The DMAMUX module provides these features Up to 63...

Page 213: ...he period of a DMA trigger Normal mode In this mode a DMA source is routed directly to the specified DMA channel The operation of the DMAMUX in this mode is completely transparent to the system Period...

Page 214: ...X_CHCFG10 8 R W 00h 11 4 1 214 4002_100B Channel Configuration register DMAMUX_CHCFG11 8 R W 00h 11 4 1 214 4002_100C Channel Configuration register DMAMUX_CHCFG12 8 R W 00h 11 4 1 214 4002_100D Chann...

Page 215: ...nal description The primary purpose of the DMAMUX is to provide flexibility in the system s use of the available DMA channels As such configuration of the DMAMUX is intended to be a static procedure d...

Page 216: ...and the actual DMA transfer cannot be guaranteed DMA channel 0 Source 1 Source 2 Source 3 Always 1 DMA channel m 1 Always y Trigger m Source x Trigger 1 Figure 11 2 DMAMUX triggered channels The DMA c...

Page 217: ...a trigger as described above After it has been set up the SPI will request DMA transfers presumably from memory as long as its transmit buffer is empty By using a trigger on this channel the SPI tran...

Page 218: ...t as possible sometimes with software activation Performing DMA transfers from memory to the external bus or vice versa Similar to memory to memory transfers this is typically done as quickly as possi...

Page 219: ...intervention 11 6 Initialization application information This section provides instructions for initializing the DMA channel MUX 11 6 1 Reset The reset state of each individual bit is shown in Memory...

Page 220: ...G ENBL and CHCFG TRIG fields of the DMA channel 3 Ensure that the DMA channel is properly configured in the DMA The DMA channel may be enabled at this point 4 Select the source to be routed to the DMA...

Page 221: ...any of the CHCFG registers Additionally some module specific configuration may be necessary See the appropriate section for more details To switch the source of a DMA channel 1 Disable the DMA channel...

Page 222: ...R 0x0009 volatile unsigned char CHCFG10 volatile unsigned char DMAMUX_BASE_ADDR 0x000A volatile unsigned char CHCFG11 volatile unsigned char DMAMUX_BASE_ADDR 0x000B volatile unsigned char CHCFG12 vola...

Page 223: ...ssor The hardware microarchitecture includes A DMA engine that performs Source address and destination address calculations Data movement operations Local memory containing transfer control descriptor...

Page 224: ...channels provide the same functionality This structure allows data transfers associated with one channel to be preempted after the completion of a read write sequence if a higher priority channel act...

Page 225: ...ual the eDMA engine performs a series of source read destination write operations until the number of bytes specified in the minor loop byte count has moved For descriptors where the sizes are not equ...

Page 226: ...nitiation Initiation via a channel to channel linking mechanism for continuous transfers Peripheral paced hardware requests one per channel Fixed priority and round robin channel arbitration Channel c...

Page 227: ...MA continues operation until the channel retires Wait Before entering Wait mode the DMA attempts to complete its current transfer After the transfer completes the device enters Wait mode 12 3 Memory m...

Page 228: ...he value of zero Writes to reserved bits in a register are ignored Reading or writing a reserved memory location generates a bus error DMA memory map Absolute address hex Register name Width in bits A...

Page 229: ...RI0 8 R W See section 12 3 21 266 4000_8104 Channel n Priority Register DMA_DCHPRI7 8 R W See section 12 3 21 266 4000_8105 Channel n Priority Register DMA_DCHPRI6 8 R W See section 12 3 21 266 4000_8...

Page 230: ...4000_901E TCD Beginning Minor Loop Link Major Loop Count Channel Linking Disabled DMA_TCD0_BITER_ELINKNO 16 R W Undefined 12 3 36 280 4000_9020 TCD Source Address DMA_TCD1_SADDR 32 R W Undefined 12 3...

Page 231: ...et DMA_TCD2_DOFF 16 R W Undefined 12 3 30 273 4000_9056 TCD Current Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD2_CITER_ELINKYES 16 R W Undefined 12 3 31 274 4000_9056 DMA_TCD2_CIT...

Page 232: ...ount Minor Loop Mapping Disabled DMA_TCD4_NBYTES_MLNO 32 R W Undefined 12 3 25 269 4000_9088 TCD Signed Minor Loop Offset Minor Loop Mapping Enabled and Offset Disabled DMA_TCD4_NBYTES_MLOFFNO 32 R W...

Page 233: ...4000_90BE TCD Beginning Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD5_BITER_ELINKYES 16 R W Undefined 12 3 35 279 4000_90BE TCD Beginning Minor Loop Link Major Loop Count Channel...

Page 234: ...3 28 272 4000_90F0 TCD Destination Address DMA_TCD7_DADDR 32 R W Undefined 12 3 29 273 4000_90F4 TCD Signed Destination Address Offset DMA_TCD7_DOFF 16 R W Undefined 12 3 30 273 4000_90F6 TCD Current...

Page 235: ...Address Offset DMA_TCD9_SOFF 16 R W Undefined 12 3 23 267 4000_9126 TCD Transfer Attributes DMA_TCD9_ATTR 16 R W Undefined 12 3 24 268 4000_9128 TCD Minor Byte Count Minor Loop Mapping Disabled DMA_TC...

Page 236: ..._9156 DMA_TCD10_CITER_ELINKNO 16 R W Undefined 12 3 32 275 4000_9158 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD10_DLASTSGA 32 R W Undefined 12 3 33 276 4000_915C TCD Contro...

Page 237: ...pping Enabled and Offset Disabled DMA_TCD12_NBYTES_MLOFFNO 32 R W Undefined 12 3 26 270 4000_9188 TCD Signed Minor Loop Offset Minor Loop Mapping and Offset Enabled DMA_TCD12_NBYTES_MLOFFYES 32 R W Un...

Page 238: ...Link Major Loop Count Channel Linking Enabled DMA_TCD13_BITER_ELINKYES 16 R W Undefined 12 3 35 279 4000_91BE TCD Beginning Minor Loop Link Major Loop Count Channel Linking Disabled DMA_TCD13_BITER_EL...

Page 239: ...91E8 TCD Signed Minor Loop Offset Minor Loop Mapping and Offset Enabled DMA_TCD15_NBYTES_MLOFFYES 32 R W Undefined 12 3 27 271 4000_91EC TCD Last Source Address Adjustment DMA_TCD15_SLAST 32 R W Undef...

Page 240: ...ddress offsets TCDn_SLAST and TCDn_DLAST_SGA are used to compute the next TCDn_SADDR and TCDn_DADDR values When minor loop mapping is enabled EMLM is 1 TCDn word2 is redefined A portion of TCDn word2...

Page 241: ...efined as a 32 bit NBYTES field 1 Enabled TCDn word2 is redefined to include individual enable fields an offset field and the NBYTES field The individual enable fields allow the minor loop offset to b...

Page 242: ...ved 12 3 6 Error Status Register DMA_ES The ES provides information concerning the last recorded channel error Channel errors can be caused by A configuration error that is An illegal setting in the t...

Page 243: ...source address configuration error 1 The last recorded error was a configuration error detected in the TCDn_SADDR field TCDn_SADDR is inconsistent with TCDn_ATTR SSIZE 6 SOE Source Offset Error 0 No...

Page 244: ...hannels to enable the request signal for each channel The state of any given channel enable is directly affected by writes to this register it is also affected by writes to the SERQ and CERQ registers...

Page 245: ...channel is disabled 1 The DMA request signal for the corresponding channel is enabled 11 ERQ11 Enable DMA Request 11 0 The DMA request signal for the corresponding channel is disabled 1 The DMA reques...

Page 246: ...DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 0 ERQ0 Enable DMA Request 0 0 The DMA request signal for the correspondin...

Page 247: ...enerate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 12 EEI12 Enable Error Interrupt 12 0 The error signal for corresponding ch...

Page 248: ...for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 3 EEI3 Enable Error Interrupt 3 0 The...

Page 249: ...byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 18h offset 4000_8018h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEE 0 CEEI Reset 0 0 0 0 0 0 0 0 DMA_C...

Page 250: ...operation ignore the other bits in this register 6 SAEE Sets All Enable Error Interrupts 0 Set only the EEI bit specified in the SEEI field 1 Sets all bits in EEI 5 4 Reserved This field is reserved S...

Page 251: ...t in ERQ 12 3 12 Set Enable Request Register DMA_SERQ The SERQ provides a simple memory mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel The data value on a...

Page 252: ...Setting the CADN bit provides a global clear function forcing all DONE bits to be cleared If the NOP bit is set the command is ignored This allows you to write multiple byte registers as a 32 bit word...

Page 253: ...you to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset...

Page 254: ...ite multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0 0 0...

Page 255: ...rite multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Fh offset 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0 0 0 0...

Page 256: ...T a 1 in any bit position clears the corresponding channel s interrupt request A zero in any bit position has no affect on the corresponding channel s current interrupt status The CINT register is pro...

Page 257: ...The interrupt request for corresponding channel is active 9 INT9 Interrupt Request 9 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is a...

Page 258: ...routed to the interrupt controller During the execution of the interrupt service routine associated with any DMA errors it is software s responsibility to clear the appropriate bit negating the error...

Page 259: ...s not occurred 1 An error in this channel has occurred 14 ERR14 Error In Channel 14 0 An error in this channel has not occurred 1 An error in this channel has occurred 13 ERR13 Error In Channel 13 0 A...

Page 260: ...in this channel has not occurred 1 An error in this channel has occurred 4 ERR4 Error In Channel 4 0 An error in this channel has not occurred 1 An error in this channel has occurred 3 ERR3 Error In C...

Page 261: ...re this status is affected by the ERQ bits Address 4000_8000h base 34h offset 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12...

Page 262: ...ed for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardware 0 A hardware service request for...

Page 263: ...for channel 6 is not present 1 A hardware service request for channel 6 is present 5 HRS5 Hardware Request Status Channel 5 The HRS bit for its respective channel remains asserted for the period when...

Page 264: ...respective channel remains asserted for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardwar...

Page 265: ...for channel 10 1 Enable asynchronous DMA request for channel 10 9 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 0 Disable asynchronous DMA request for channel 9 1 Enable asynchron...

Page 266: ...rbitration is enabled CR ERCA 0 the contents of these registers define the unique priorities associated with each channel The channel priorities are evaluated by numeric value for example 0 is the low...

Page 267: ...Source Address DMA_TCDn_SADDR Address 4000_8000h base 1000h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SADDR W Reset x...

Page 268: ...queue easily For data queues requiring power of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the queue freezing the des...

Page 269: ...2 1 0 R NBYTES W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_NBYTES_MLNO field descriptions Field Description NBYTES Minor Byte Transfer C...

Page 270: ...ss 4000_8000h base 1008h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE NBYTES W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5...

Page 271: ...Offset Minor Loop Mapping and Offset Enabled DMA_TCDn_NBYTES_MLOFFYES One of three registers this register TCD_NBYTES_MLNO or TCD_NBYTES_MLOFFNO defines the number of bytes to transfer per request Whi...

Page 272: ...nt has transferred This is an indivisible operation and cannot be halted It can however be stalled by using the bandwidth control field or via preemption After the minor count is exhausted the SADDR a...

Page 273: ...he destination data 12 3 30 TCD Signed Destination Address Offset DMA_TCDn_DOFF Address 4000_8000h base 1014h offset 32d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DOFF Write R...

Page 274: ...annel linking NOTE This bit must be equal to the BITER ELINK bit otherwise a configuration error is reported 0 The channel to channel linking is disabled 1 The channel to channel linking is enabled 14...

Page 275: ...nables linking to another channel defined by the LINKCH field The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specified ch...

Page 276: ...x x x x x x x x x Notes x Undefined at reset DMA_TCDn_DLASTSGA field descriptions Field Description DLASTSGA Destination last address adjustment or the memory address for the next transfer control des...

Page 277: ...and after the last write of each minor loop This behavior is a side effect of reducing start up latency 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for 4 cycles after each R W 11 eDMA e...

Page 278: ...ormat 1 The current channel s TCD specifies a scatter gather format The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execu...

Page 279: ...ng on minor loop complete As the channel completes the minor loop this flag enables the linking to another channel defined by BITER LINKCH The link target channel initiates a channel service request v...

Page 280: ...R field If the channel is configured to execute a single service request the initial values of BITER and CITER should be 0x0001 12 3 36 TCD Beginning Minor Loop Link Major Loop Count Channel Linking D...

Page 281: ...d the contents of this field are reloaded into the CITER field NOTE When the software loads the TCD this field must be set equal to the corresponding CITER field otherwise a configuration error is rep...

Page 282: ...he control module then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is complete...

Page 283: ...g continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic performs the requ...

Page 284: ...tting in the transfer control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is reported...

Page 285: ...the scatter gather address DLAST_SGA is not aligned on a 32 byte boundary If minor loop channel linking is enabled upon channel completion a configuration error is reported when the link is attempted...

Page 286: ...ransfer in the event the full data transfer is no longer needed The cancel transfer bit does not abort the channel It simply stops the transferring of data and then retires the channel through its nor...

Page 287: ...allows for a pool of low priority large data moving channels to be defined These low priority channels can be configured to not preempt each other thus preventing a low priority channel from consuming...

Page 288: ...7 MHz 32 bit 133 3 66 7 53 3 83 3 MHz 32 bit 166 7 83 3 66 7 100 0 MHz 32 bit 200 0 100 0 80 0 133 3 MHz 32 bit 266 7 133 3 106 7 150 0 MHz 32 bit 300 0 150 0 120 0 Internal SRAM to internal SRAM tra...

Page 289: ...local memory Depending on the state of the crossbar switch arbitration at the system bus may insert an additional cycle of delay here 8 11 8 12 The last part of the TCD is read in This cycle represen...

Page 290: ...ands Operand Description PEAKreq Peak request rate freq System frequency entry Channel startup 4 cycles read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during...

Page 291: ...eDMA peripheral request signals For the peak request rate calculations above the arbitration and request registering is absorbed in or overlaps the previous executing channel Note When channel linking...

Page 292: ...the major loop is exhausted further post processing executes such as interrupts major loop channel linking and scatter gather operations if enabled Table 12 8 TCD Control and Status fields TCDn_CSR f...

Page 293: ...s added to current address after each transfer often the same value as xSIZE Each DMA source S and destination D has its own Address xADDR Size xSIZE Offset xOFF Modulo xMOD Last Address Adjustment xL...

Page 294: ...iderations for the eDMA 12 5 3 1 Fixed channel arbitration In this mode the channel service request from the highest priority channel is selected to execute 12 5 3 2 Round robin channel arbitration Ch...

Page 295: ...e TCDn_CSR START bit requests channel service 2 The channel is selected by arbitration for servicing 3 eDMA engine writes TCDn_CSR DONE 0 TCDn_CSR START 0 TCDn_CSR ACTIVE 1 4 eDMA engine reads channel...

Page 296: ...LAST 32 TCDn_DLAST_SGA 32 This would generate the following sequence of events 1 First hardware that is eDMA peripheral request for channel service 2 The channel is selected by arbitration for servici...

Page 297: ...nsfers are executed as follows a Read byte from location 0x1010 read byte from location 0x1011 read byte from 0x1012 read byte from 0x1013 b Write 32 bits to location 0x2010 first iteration of the min...

Page 298: ...circular buffer is created where the address wraps to the original value while the 28 upper address bits 0x1234567x retain their original value In this example the source address is set to 0x12345670...

Page 299: ...model The TCD status bits execute the following sequence for a hardware activated channel Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware peripheral request a...

Page 300: ...simultaneously in the global TCD map a higher priority channel is actively preempting a lower priority channel 12 5 6 Channel Linking Channel linking or chaining is a mechanism where one channel sets...

Page 301: ...ble summarizes how a DMA channel can link to another DMA channel i e use another channel s TCD at the end of a loop Table 12 10 Channel Linking Parameters Desired Link Behavior TCD Control Field Name...

Page 302: ...D major e_link would be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The following coherency model is recommended when executing a...

Page 303: ...he major linkch field and the e_sg bit with a single read For both dynamic channel linking and scatter gather requests the TCD local memory controller forces the TCD major e_link and TCD e_sg bits to...

Page 304: ...jor loop channel linking For a channel using major loop channel linking the coherency model described here may be used for a dynamic scatter gather request This method uses the TCD dlast_sga field as...

Page 305: ...channel 1 Stop the DMA service request at the peripheral first Confirm it has been disabled by reading back the appropriate register in the peripheral 2 Check Hardware Request Status Register DMA_HRS...

Page 306: ...cessed and the HRS bit reads zero 12 6 Usage Guide NOTE User should configure DMA_TCDn_CSR BWC bit 15 14 as 10 when another DMA channel is active Related application notes on this DMA module are as fo...

Page 307: ...herals which are located in one 4G bytes 32 bit address contiguous memory space This chapter describes the memory and peripheral locations within that memory space The following figure shows the syste...

Page 308: ...00 0x4007_5000 0x4007_E000 0x4007_4000 0x4007_FFFF 0x4007_F000 0x4007_D000 0x4000_1000 0x4000_0000 0x07FF_FFFF 0x0000_0000 0x4008_0000 eDMA ADC1 0x4003_6000 0x4006_3000 TRGMUX1 0x4006_A000 0x4006_B000...

Page 309: ...of FlexNVM consisting of 2 KB sectors 1 block 4 KB of FlexRAM The amounts of flash memory and the address range for the devices is shown in following table Device Program flash KB FlexNVM KB FlexRAM...

Page 310: ...x M4 architecture NOTE Burst access cannot occur across the 0x2000_0000 boundary that separates the two SRAM arrays The two arrays should be treated as separate memory ranges for burst accesses The am...

Page 311: ...core master non core master non core master Frontdoor MPU MPU Figure 13 2 SRAM access diagram The following simultaneous accesses can be made to different logical regions of the SRAM Core code and cor...

Page 312: ...ace to support single bit insert and extract operations from the processor Table 13 1 System memory map System 32 bit Address Range Destination Slave Access 0x0000_0000 0x07FF_FFFF 1 Program flash and...

Page 313: ...ce is limited to the core DMA 2 ARM Cortex M4 core access privileges also includes accesses via the debug interface 3 The SRAM on this device could be accessed through normal way with 32 bit operation...

Page 314: ...idge The peripheral bridge converts register access from AHB bus domain to peripheral bus domain For peripherals that have clock gating control bits CGC bit in PCC module the associated peripherals co...

Page 315: ...x4000_B000 11 0x4000_C000 12 0x4000_D000 13 MPU 0x4000_E000 14 0x4000_F000 15 RGPIO controller aliased to 0x400F_F000 0x4001_0000 16 0x4001_1000 17 0x4001_2000 18 0x4001_3000 19 0x4001_4000 20 0x4001_...

Page 316: ...0 52 0x4003_5000 53 0x4003_6000 54 Programmable delay block PDB 0 0x4003_7000 55 Low power Periodic interrupt timer LPIT0 0x4003_8000 56 FlexTimer FTM 0 0x4003_9000 57 FlexTimer FTM 1 0x4003_A000 58 F...

Page 317: ...0x4005_C000 92 0x4005_D000 93 0x4005_E000 94 0x4005_F000 95 0x4006_0000 96 OSC32 0x4006_1000 97 External watchdog EWM 0x4006_2000 98 Trigger Multiplexing Control TRGMUX 0 0x4006_3000 99 Trigger Multip...

Page 318: ...ess to select processor local modules These resources are only accessible from the core other system masters do not have access to them Table 13 3 PPB memory map System 32 bit Address Range Resource 0...

Page 319: ...08_3000 0xE00F_EFFF Reserved 0xE00F_F000 0xE00F_FFFF ARM Core ROM Table1 allows auto detection of debug components 1 The ARM Core ROM table is optionally required by ARM CoreSight debug infrastructure...

Page 320: ...Private Peripheral Bus PPB memory map Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 320 NXP Semiconductors...

Page 321: ...FF FlexNVM R2 Write through and cacheable 1 0x1400_0000 0x17FF_FFFF FlexRAM Non cacheable 0x1800_0000 0x1BFF_FFFF Reserved region R3 0x1C00_0000 0x1C00_3FFF Boot ROM Write through always 0x1C00_4000 0...

Page 322: ...memories provide zero wait state access to RAM and cacheable address spaces The local memory controller includes three memory controllers and their attached memories SRAM lower SRAM_L controller via...

Page 323: ...aces are device specific See the chip specific LMEM information for the address space decode details 14 2 2 Cache features A cache is a block of high speed memory locations containing address informat...

Page 324: ...orts the following modes of operation 1 Write through access to address spaces with this cache mode are cacheable A write through read miss on the input bus causes a line read on the output bus of a 1...

Page 325: ...14 3 5 330 14 3 1 Cache control register LMEM_PCCCR Address E008_2000h base 0h offset E008_2000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R GO 0 PUSHW1 INVW1 PUSHW0 INVW0 0 W Reset 0 0 0 0...

Page 326: ...d lines in way 0 and invalidate all lines in way 0 clear way 0 0 No operation 1 When setting the GO bit invalidate all lines in way 0 23 4 Reserved This field is reserved This read only field is reser...

Page 327: ...rved This read only field is reserved and always has the value 0 27 LACC Line access type 0 Read 1 Write 26 LADSEL Line Address Select When using the cache address the way must also be specified in CL...

Page 328: ...his bit reads zero 19 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 TDSEL Tag Data Select Selects tag or data for search and read or write commands...

Page 329: ...ss CSAR 31 12 bits are used for tag compare CSAR 11 4 bits are used to access the tag arrays CSAR 11 2 bits are used to access the data arrays 1 Reserved This field is reserved This read only field is...

Page 330: ...er LMEM_PCCRMR The CRMR register allows you to demote the cache mode of various subregions within the device s memory map Demoting the cache mode reduces the cache function applied to a memory region...

Page 331: ...ion 1 00 Non cacheable 01 Non cacheable 10 Write through 11 Write back 27 26 R2 Region 2 mode Controls the cache mode for region 2 00 Non cacheable 01 Non cacheable 10 Write through 11 Write back 25 2...

Page 332: ...gion 8 00 Non cacheable 01 Non cacheable 10 Write through 11 Write back 13 12 R9 Region 9 mode Controls the cache mode for region 9 00 Non cacheable 01 Non cacheable 10 Write through 11 Write back 11...

Page 333: ...e 01 Non cacheable 10 Write through 11 Write back R15 Region 15 mode Controls the cache mode for region 15 00 Non cacheable 01 Non cacheable 10 Write through 11 Write back 14 4 Functional Description...

Page 334: ...ng the non cacheable cache write through cache miss and cache maintenance accesses to the CCM bus and the crossbar switch using the Master0 port 14 4 1 2 Processor System accesses Processor System acc...

Page 335: ...ZE do not have to be equal For example if SRAM_L size is 32 KBytes and SRAM_U size is 64 KBytes Valid address ranges for SRAM_L and SRAM_U are then defined as SRAM_L 0x20000_0000 32 KBytes 0x1fff_ffff...

Page 336: ...L U arbitration is controlled by the SRAM controller based on the configuration bits in the MCM module NOTE Burst access cannot occur across the 0x2000_0000 boundary that separates the two SRAM arrays...

Page 337: ...select the byte within the 32 bit word 14 4 4 Cache Control The Code Cache is disabled at reset Cache tag and data arrays are not cleared at reset Therefore to enable the cache cache commands must be...

Page 338: ...l way 1 push all way 0 0 1 1 1 Invalidate all way 1 clear all way 0 1 0 0 0 Push all way 1 1 0 0 1 Push all way 1 invalidate all way 0 1 0 1 0 Push all way 1 push all way 0 push cache 1 0 1 1 Push all...

Page 339: ...ys set while the command is active and is cleared by the hardware when the command completes The CLCR 27 24 bits select the line command as follows Table 14 3 Cache Line Commands CLCR 27 24 Command LA...

Page 340: ...a or at bit 4 to step through lines and Set the line command go bit CSAR LGO The line command go bit is shared between the CLCR and CSAR registers so that the above steps can be completed in a single...

Page 341: ...ot modified 1 1 0 Way 1 line was invalid No hit 1 1 1 Way 1 valid and modified Way 1 valid and modified At completion of a line command other than a write the CCVR Cache R W Value Register contains in...

Page 342: ...Functional Description Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 342 NXP Semiconductors...

Page 343: ...ally the core accesses configuration information from a common set of peripheral addresses and the chip configuration logic properly evaluates based on the requesting processor and returns the appropr...

Page 344: ...ection page 4000_1000 Processor X Type Register MSCM_CPxTYPE 32 R See section 15 3 2 345 4000_1004 Processor X Number Register MSCM_CPxNUM 32 R See section 15 3 3 346 4000_1008 Processor X Master Regi...

Page 345: ...The 32 bit response includes 3 ASCII characters defining the CPU type along with a byte defining the logical revision number The logical revision number follows ARM s rYpZ nomenclature Address 4000_10...

Page 346: ...served This field is reserved This read only field is reserved and always has the value 0 0 CPN Processor x Number This zero filled word defines the logical processor number for CPx NOTE If single cor...

Page 347: ...cessor X Count Register MSCM_CPxCOUNT The register provides a CPU specific response indicating the total number of processor cores in the chip configuration Address 4000_1000h base Ch offset 4000_100C...

Page 348: ...ription 31 24 ICSZ Level 1 Instruction Cache Size This read only field provides an encoded value of the Instruction Cache size The capacity of the memory is expressed as Size bytes 2 9 SZ where SZ is...

Page 349: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PERSONALITY RYPZ W Reset Notes PERSONALITY field See bit field description RYPZ field See bit field description MSCM_CP0TYPE field descriptions Field D...

Page 350: ...ed This field is reserved This read only field is reserved and always has the value 0 0 CPN Processor x Number This zero filled word defines the logical processor number for CPx If single core configu...

Page 351: ...0 Count Register MSCM_CP0COUNT The register provides a CPU specific response indicating the total number of processor cores in the chip configuration Address 4000_1000h base 2Ch offset 4000_102Ch Bit...

Page 352: ...ption 31 24 ICSZ Level 1 Instruction Cache Size This read only field provides an encoded value of the Instruction Cache size The capacity of the memory is expressed as Size bytes 2 9 SZ where SZ is no...

Page 353: ...n all zeroes Privileged writes from a processor core or the debugger to writeable registers update the appropriate fields Privileged writes from other bus masters are ignored Attempted user mode acces...

Page 354: ...ld defines the validity presence of the on chip memory 0 OCMEMn is not present 1 OCMEMn is present 30 Reserved This field is reserved 29 Reserved This field is reserved 28 OCMSZH OCMEM Size Hole For o...

Page 355: ...CMEMn 128 bits wide 101 OCMEMn 256 bits wide 110 111 Reserved 16 RO Read Only This register bit provides a mechanism to lock the configuration state defined by OCMDRn 11 0 Once asserted attempted writ...

Page 356: ...ches or speculative accesses are initiated in response to instruction fetches or data references OCMDR bit 4 data prefetch Value 0 means enable and value 1 means disable OCMDR bit 5 flash speculate Va...

Page 357: ...28 bit flash memory location 16 1 2 Modes of operation The FAU operates only when a bus master accesses the program flash memory or FlexMemory In terms of chip power modes The FAU operates only in Run...

Page 358: ...help to reduce or even eliminate wait states when accessing sequential code and or data For example consider the following scenario Assume a system with a 4 1 core to flash clock ratio and with specul...

Page 359: ...venth and eighth longwords takes only 1 clock each because the data is already available inside the FAU 16 2 Usage Guide For many systems the on chip flash is the main memory The Flash Acceleration Un...

Page 360: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 360 NXP Semiconductors...

Page 361: ...xported from ROM for customer use Please visit http www nxp com kboot for more information 17 2 Introduction The FTFE module includes the following accessible memory regions Program flash memory for v...

Page 362: ...to degradation of the erased 1 states and or programmed 0 states Therefore it is recommended that each flash block or sector be re erased immediately prior to factory programming to ensure that the f...

Page 363: ...aditional RAM operations When configured for EEPROM Protection scheme prevents accidental program or erase of data written for EEPROM Built in hardware emulation scheme to automate EEPROM record maint...

Page 364: ...access Memory controller Program flash 0 FlexRAM EEPROM backup Data flash 0 Figure 17 1 FTFE block diagram 17 2 3 Glossary Command write sequence A series of MCU writes to the Flash FCCOB register gr...

Page 365: ...tor The EEPROM backup data sector contains one EEPROM header and up to 255 EEPROM backup data records which are used by the EEPROM filing system Endurance The number of times that a flash memory locat...

Page 366: ...bits of data with an aligned word having byte address 0 0 Program flash The program flash memory provides nonvolatile storage for vectors and code store Program flash sector The smallest portion of th...

Page 367: ...ecific memory map for the location of the program flash memory Flash Configuration Field Offset Address Size Bytes Field Description 0x0_0400 0x0_0407 8 Backdoor Comparison Key Refer to Verify Backdoo...

Page 368: ...XACCL 2 Field index 0x09 0x3B0 0x3B3 4 Program Once SACCH 1 Field index 0x0A 0x3B4 0x3B7 4 Program Once SACCL 1 Field index 0x0A 0x3B8 0x3BB 4 Program Once SACCH 2 Field index 0x0B 0x3BC 0x3BF 4 Prog...

Page 369: ...during the flash reset sequence To program the EEERST EEESIZE value see the Program Partition command described in Program Partition command Table 17 1 EEPROM Data Set Size Data flash IFR 0x03FD 7 6...

Page 370: ...exNVM partition code The FlexNVM partition code byte in the data flash 0 IFR supplies a code which specifies how to split the FlexNVM block between data flash memory and EEPROM backup memory supportin...

Page 371: ...1011 32 32 1100 64 0 1101 Reserved Reserved 1110 Reserved Reserved 1111 64 0 17 4 4 Register descriptions The FTFE module contains a set of memory mapped control and status registers NOTE While a comm...

Page 372: ...bject Registers FTFE_FCCOB5 8 R W 00h 17 4 4 5 379 4002_000B Flash Common Command Object Registers FTFE_FCCOB4 8 R W 00h 17 4 4 5 379 4002_000C Flash Common Command Object Registers FTFE_FCCOBB 8 R W...

Page 373: ...R Undefined 17 4 4 10 385 4002_0022 Supervisor only Access Registers FTFE_SACCH1 8 R Undefined 17 4 4 10 385 4002_0023 Supervisor only Access Registers FTFE_SACCH0 8 R Undefined 17 4 4 10 385 4002_00...

Page 374: ...ization sequence Depending on how quickly the read occurs after reset release the user may or may not see the 0 hardware reset value 0 FTFE command or EEPROM file system operation in progress 1 FTFE c...

Page 375: ...CCIF 1 and before the next command has been launched At some point during the execution of command N 1 the previous result is discarded and any previous error is cleared 17 4 4 2 Flash Configuration...

Page 376: ...only field is reserved and always has the value 0 2 PFLSH FTFE configuration 0 FTFE configuration supports one program flash block and one FlexNVM block 1 Reserved 1 RAMRDY RAM Ready This flag indicat...

Page 377: ...lue Address 4002_0000h base 2h offset 4002_0002h Bit 7 6 5 4 3 2 1 0 Read KEYEN MEEN FSLACC SEC Write Reset x x x x x x x x Notes x Undefined at reset FTFE_FSEC field descriptions Field Description 7...

Page 378: ...es The limitations are defined per device and are detailed in the Chip Configuration details If the FTFE module is unsecured using backdoor key access the SEC bits are forced to 10b 00 MCU security st...

Page 379: ...rs the CCIF bit which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes CCIF returns to 1 No command buffering or queueing is provided the next comman...

Page 380: ...egions are protected from program and erase operations Protected flash regions cannot have their content changed that is these regions cannot be programmed and cannot be erased by any FTFE command Unp...

Page 381: ...hat currently unprotected memory can be protected but currently protected memory cannot be unprotected Since unprotected regions are marked with a 1 and protected regions use a 0 only writes changing...

Page 382: ...ut currently protected memory cannot be unprotected Since unprotected regions are marked with a 1 and protected regions use a 0 only writes changing 1s to 0s are accepted This 1 to 0 transition check...

Page 383: ...nce unprotected regions are marked with a 1 and protected regions use a 0 only writes changing 1s to 0s are accepted This 1 to 0 transition check is performed on a bit by bit basis Those FDPROT bits w...

Page 384: ...with the logical AND of Program Flash IFR addresses A and B as indicated in the following table Execute only access register Program Flash IFR address A Program Flash IFR address B XACCH0 0x03A3 0x03...

Page 385: ...3 56 SACCH1 SA 55 48 SACCH2 SA 47 40 SACCH3 SA 39 32 SACCL0 SA 31 24 SACCL1 SA 23 16 SACCL2 SA 15 8 SACCL3 SA 7 0 During the reset sequence the SACC registers are loaded with the logical AND of Progra...

Page 386: ...into the SACC and XACC bitmaps to get the appropriate permission flags All bits in the register are read only The contents of this register are loaded during the reset sequence Address 4002_0000h base...

Page 387: ...er are loaded during the reset sequence Address 4002_0000h base 2Bh offset 4002_002Bh Bit 7 6 5 4 3 2 1 0 Read NUMSG Write Reset x x x x x x x x Notes x Undefined at reset FTFE_FACSN field description...

Page 388: ...DIF flag is cleared by writing a 1 to it Writing a 0 to DFDIF has no effect 0 Double bit fault not detected during a valid flash read access from the platform flash controller 1 Double bit fault detec...

Page 389: ...Fault Detect Interrupt Enable The DFDIE bit controls interrupt generation when an uncorrectable ECC fault is detected during a valid flash read access from the platform flash controller 0 Double bit...

Page 390: ...e data flash memory as shown in the following figure Data flash size 8 DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 DPROT7 DPROT6 FlexNVM Last data flash address Data flash size 8 Data flash size 8 Dat...

Page 391: ...ce 17 5 2 Flash Access Protection Individual segments within the program flash memory can be designated for restricted access Specific flash commands Program Check Program Phrase Erase Flash Block Era...

Page 392: ...ments of the program flash memory as shown in the following figure Program flash size 64 SACCL3 SA0 0x0_0000 Program flash Last program flash address Program flash size 64 SACCL3 SA1 Program flash siz...

Page 393: ...EEPROM User Perspective The EEPROM system is shown in the following figure File system handler User access effective EEPROM FlexRAM EEPROM backup with 2KByte erase sectors Figure 17 7 Top Level EEPRO...

Page 394: ...to quickly store large amounts of data or store data that is static The EEPROM partition in FlexRAM is useful for storing smaller amounts of data that will be changed often DEPART Data flash EEPROM ba...

Page 395: ...ed for erase 17 5 3 4 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash the EEPROM data set size can be set to any of several non zero values The byte...

Page 396: ...generate interrupt requests to the MCU upon the occurrence of various FTFE events These interrupt events and their associated status and control bits are shown in the following table Table 17 5 FTFE...

Page 397: ...rrupts 17 5 5 2 Stop Mode When the MCU requests stop mode if an FTFE command is active CCIF 0 the command execution completes before the MCU is allowed to enter stop mode CAUTION The MCU should never...

Page 398: ...from data flash and FlexRAM while program and erase commands are executing on the program flash When configured as traditional RAM writes to the FlexRAM are allowed during data flash operations Simult...

Page 399: ...ACCERR flag being set 17 5 9 1 1 Load the FCCOB Registers The user must load the FCCOB registers with all parameters required by the desired FTFE command The individual registers that make up the FCC...

Page 400: ...ter or protection step fails Instead command processing is terminated after setting the FSTAT CCIF bit 2 If the parameter and protection checks pass the command proceeds to execution Run time errors s...

Page 401: ...Read FSTAT register no yes Bit Polling for Command Completion Check Figure 17 10 Generic Flash Command Write Sequence Flowchart 17 5 9 2 Flash commands The following table summarizes the function of...

Page 402: ...a program flash block or data flash block An erase of any flash block is only possible when unprotected FlexNVM block must not be partitioned for EEPROM 0x09 Erase Flash Sector Erase all bytes in a pr...

Page 403: ...security keys to those stored in the program flash 0x49 Erase All Blocks Unsecure Erase all program flash blocks data flash blocks FlexRAM EEPROM backup data records and data flash IFR Then verify era...

Page 404: ...sly on the program flash data flash and FlexRAM memories Some operations cannot be executed simultaneously because certain hardware resources are shared by the memories The priority has been placed on...

Page 405: ...ead These non standard read levels are applied only during the command execution All simple uncommanded flash array reads to the MCU always use the standard un margined read reference level Only the n...

Page 406: ...be used during verify of the initial factory programming 17 5 11 Flash command descriptions This section describes all flash commands that can be launched by a command write sequence The FTFE sets the...

Page 407: ...unch the Read 1s Block command the FTFE sets the read margin for 1s according to Table 17 8 and then reads all locations within the selected program flash or data flash block When the data flash is ta...

Page 408: ...SEC 1 Flash address 23 16 of the first double phrase to be verified for program flash phrase for data flash 2 Flash address 15 8 of the first double phrase to be verified for program flash phrase for...

Page 409: ...0 17 5 11 3 Program Check command The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level Table 17 13 Pr...

Page 410: ...x02 Read at Factory margin 1 and Factory margin 0 Table 17 15 Program Check Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR An invalid flas...

Page 411: ...es 0x00_0008 0x00_000F After clearing CCIF to launch the Read Resource command eight consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB regi...

Page 412: ...program value A Byte 6 program value B Byte 7 program value 1 Must be 64 bit aligned Flash address 2 0 000 Upon clearing CCIF to launch the Program Phrase command the FTFE programs the data bytes int...

Page 413: ...FCCOB Contents 7 0 0 0x08 ERSBLK 1 Flash address 23 16 in the flash block to be erased 2 Flash address 15 8 in the flash block to be erased 3 Flash address 7 0 1 in the flash block to be erased 1 Must...

Page 414: ...ents 7 0 0 0x09 ERSSCR 1 Flash address 23 16 in the flash sector to be erased 2 Flash address 15 8 in the flash sector to be erased 3 Flash address 7 0 1 in the flash sector to be erased 1 Must be 128...

Page 415: ...en made the FTFE clears the ERSSUSP bit prior to setting CCIF When an Erase Flash Sector operation has been successfully suspended the FTFE sets CCIF and leaves the ERSSUSP bit set While CCIF is set t...

Page 416: ...G ERSSUSP is set a write to the FlexRAM while FCNFG EEERDY is set clears ERSSUSP and aborts the suspended operation The FlexRAM write operation is executed by the FTFE Note Aborting the erase leaves t...

Page 417: ...ecute Yes DONE No ERSSUSP 1 SaveEraseAlgo Set CCIF No Yes Start New ResumeErase No Abort User Cmd Interrupt Suspend Set SUSP ACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Completed E...

Page 418: ...Section Command FCCOB Requirements FCCOB Number FCCOB Contents 7 0 0 0x0B PGMSEC 1 Flash address 23 16 2 Flash address 15 8 3 Flash address 7 0 1 4 Number of double phrases for program flash phrases f...

Page 419: ...programming The process of programming an entire flash sector using the Program Section command is as follows 1 If required execute the Set FlexRAM Function command to make the FlexRAM available as t...

Page 420: ...urity byte in the flash configuration field see Flash configuration field description remains unaffected by the Read 1s All Blocks command If the read fails i e all flash memory resources are not in t...

Page 421: ...gram Once byte 6 value B Program Once byte 7 value After clearing CCIF to launch the Read Once command an 8 byte Program Once record is read from the program flash 0 IFR index 0x00 to 0x0B and stored...

Page 422: ...selected record is programmed using the values provided into the program flash 0 IFR index 0x00 to 0x0B The Program Once command also verifies that the programmed values read back correctly Any attemp...

Page 423: ...r the Erase All Blocks operation completes Access control determined by the contents of the FXACC registers will not block execution of the Erase All Blocks command While most Flash memory will be era...

Page 424: ...the erase all request is reflected in the FCNFG ERSAREQ bit The FCNFG ERSAREQ bit is cleared once the operation completes and the normal FSTAT error reporting except FPVIOL is available as described i...

Page 425: ...rect backdoor key is supplied FSTAT ACCERR Backdoor key access has not been enabled see the description of the FSEC register FSTAT ACCERR This command is launched and the backdoor key has mismatched s...

Page 426: ...Table 17 39 Erase All Blocks Unsecure Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR Any errors have been encountered during erase or pro...

Page 427: ...An invalid margin choice is specified FSTAT ACCERR Read 1s fails FSTAT MGSTAT0 17 5 11 16 Erase All Execute only Segments command The Erase All Execute only Segments operation erases all program flas...

Page 428: ...en encountered during the verify operation FSTAT MGSTAT0 17 5 11 17 Program Partition command The Program Partition command prepares the FlexNVM block for use as data flash EEPROM backup or a combinat...

Page 429: ...e FlexNVM Partition Code is set for no EEPROM Table 17 47 Valid FlexNVM Partition Codes FlexNVM Partition Code DEPART FCCOB5 3 0 1 Data flash Size Kbytes EEPROM backup Size Kbytes 0000 64 0 0011 32 32...

Page 430: ...ntered see Table 17 46 for valid codes FSTAT ACCERR Invalid FlexNVM Partition Code is entered see Table 17 47 for valid codes FSTAT ACCERR FlexNVM Partition Code full data flash no EEPROM and EEPROM D...

Page 431: ...flash memory need to be programmed e g during factory programming the FlexRAM can be used as the Section Program Buffer for the Program Section command see Program Section command When making the Flex...

Page 432: ...amming the security byte of the flash configuration field This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region...

Page 433: ...y matched the MCU is unsecured by changing the FSEC SEC bits A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only It does not alter the secur...

Page 434: ...being erased is not guaranteed Commands and operations do not automatically resume after exiting reset 17 7 Usage Guide Related application notes on this FTFE module are as follows Production Flash Pr...

Page 435: ...racy System Oscillator SOSC and PLL It controls which clock source is used to derive the system clocks The SCG also divides the selected clock source into a variety of clock domains including the cloc...

Page 436: ...ORT Control CRC 8 bit DAC ACMPx DMAMUX eDMA PDB TCLK2 TCLK1 TCLK0 FTMx PWT SCG_xCCR SCS PLL_CLK SIRC_CLK FIRC_CLK SOSC_CLK SIM_CHIPCTL CLKOUTSEL RTC_CR LPOS SIM_CHIPCTL RTC_CLKSEL SCG_CLKOUTCNFG CLKOU...

Page 437: ...us clock through pin for external devices or diagnostics 1 For WDOG its SOSC_CLK is with no dividers For other peripherals LPUART etc its SOSC_CLK is divided by DIVx 18 4 Typical Clock Configuration T...

Page 438: ...E_CLK 100 MHz SYS_CLK 100 MHz BUS_CLK 50 MHz FLASH_CLK 25 MHz Option Slow RUN typically using the undivided FIRC Clock Frequency CORE_CLK 48 MHz SYS_CLK 48 MHz BUS_CLK 48 MHz FLASH_CLK 24 MHz Option V...

Page 439: ...ny reset PCC disables part of the clock to the corresponding module to conserve power Prior to initializing a module set the corresponding clock gating control bits in PCC register to enable the clock...

Page 440: ...t 40 MHz from OSC Timers LPTMR Yes SIRC_CLK FIRC_C LK SPLL_CLK SOSC_ CLK LPO_CLK OSC32_CLK Max BUS_CLK LPO_CLK 128kHz LPIT Yes SIRC_CLK FIRC_C LK SPLL_CLK SOSC_ CLK Max BUS_CLK RTC Yes LPO_CLK OSC32_C...

Page 441: ...SC_CLK Max 50 MHz DAC0 Yes BUS_CLK Max BUS_CLK ACMP0 ACMP2 Yes BUS_CLK Max BUS_CLK 1 The clock sources undergo clock divider DIVx in SCG For details see the High Level clocking diagram section in the...

Page 442: ...g Information The following figure shows the input clock sources available for this module Peripheral Clocking ADC PCC_ADCx CGC PCC module DIV2 DIV2 DIV2 DIV2 SOSC PLL FIRC SIRC SCG module SCG DIVBUS...

Page 443: ...k Registers SIM_FTMOPT0 FTMxCLKSEL TCLK0 TCLK1 TCLK2 10 01 11 Counter DIV1 SOSC PLL FIRC SIRC PLLDIV1_CLK SOSCDIV1_CLK SIRCDIV1_CLK FIRCDIV1_CLK PCC_FLEXTMRx PCS see PCC chapter for detailed setting D...

Page 444: ...IRCDIV2_CLK LPTMRx module BUS_CLK LPO_CLK OSC32_CLK x LPTMRx_PSR PCS Peripheral Interface Clock PCC_LPTMRx PCS 00 01 10 11 see PCC chapter for detailed setting Registers NOTE The chosen clock must rem...

Page 445: ...KSEL 18 6 9 FlexCAN Clocking Information The following figure shows the input clock sources available for this module Peripheral Clocking FlexCAN PCC_FLEXCANx CGC PCC module DIV2 SOSC SCG module SCG D...

Page 446: ...DIV2 DIV2 DIV2 SOSC PLL FIRC SIRC SCG module SCG DIVBUS PLLDIV2_CLK SOSCDIV2_CLK SIRCDIV2_CLK FIRCDIV2_CLK LPUARTx module BUS_CLK Peripheral Interface Clock PCC_LPUARTx PCS see PCC chapter for detail...

Page 447: ...d configured with the SCG_SOSCCFG EREFS bit For the supported frequency range of OSC see the Oscillator electrical specifications section in the Data Sheet For this device low frequency range 32 kHz 4...

Page 448: ...clocks of the MCU The SCG contains a system phase locked loop SPLL a slow internal reference clock SIRC a fast internal reference clock FIRC and the system oscillator clock SOSC The SPLL is sourced by...

Page 449: ...Internal reference clock IRC generators Fast IRC clock with programmable High and Low frequency range Fast clock can be used as a source for System PLL Either the slow or the fast clock can be selecte...

Page 450: ...4006_401C HSRUN Clock Control Register SCG_HCCR 32 R W See section 19 3 6 459 4006_4020 SCG CLKOUT Configuration Register SCG_CLKOUTCNFG 32 R W 0300_0000h 19 3 7 461 4006_4100 System OSC Control Stat...

Page 451: ...criptions Field Description VERSION SCG Version Number 19 3 2 Parameter Register SCG_PARAM Note Writing to this register will result in a transfer error Address 4006_4000h base 4h offset 4006_4004h Bi...

Page 452: ...clock dividers for the core DIVCORE and peripheral interface clock DIVSLOW The SCG_CSR reflects the configuration set by one of three clock control registers SCG_RCCR SCG_VCCR SCG_HCCR Note Writing t...

Page 453: ...y 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 111...

Page 454: ...tten using a 32 bit write Selecting a different clock source when in RUN requires that clock source to be enabled first and be valid before system clocks switch to that clock source If system clock di...

Page 455: ...This read only field is reserved and always has the value 0 19 16 DIVCORE Core Clock Divide Ratio 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6...

Page 456: ...Divide by 15 1111 Divide by 16 DIVSLOW Slow Clock Divide Ratio 0000 Reserved 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 100...

Page 457: ...er FOPT bits that get uploaded during reset The two option reset values are div by 4 and div by 8 SCG_VCCR field descriptions Field Description 31 28 Reserved This field is reserved This read only fie...

Page 458: ...reserved and always has the value 0 7 4 DIVBUS Bus Clock Divide Ratio 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide...

Page 459: ...e 1Ch offset 4006_401Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SCS 0 DIVCORE Reserved 0 DIVBUS DIVSLOW W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0...

Page 460: ...are should write 0 to these bits to maintain compatibility This field is reserved 11 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 4 DIVBUS Bus Clock...

Page 461: ...2 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLKOUTSEL 0 W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_CLKOUTCNFG field descriptions Field Description 31 28 Reserved This field is res...

Page 462: ...ld This flag is reset on Chip POR only SCG_SOSCCSR field descriptions Field Description 31 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 SOSCERR Sys...

Page 463: ...also disabled in the low power mode When the clock monitor is disabled in a low power mode it remains disabled until the clock valid flag is set following exit from the low power mode 0 System OSC Clo...

Page 464: ...0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SOSCDIV2 0 SOSCDIV1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_SOSCDIV field descriptions Field Description 31 19 Reserved This fie...

Page 465: ...to this register are ignored and there is no transfer error Address 4006_4000h base 108h offset 4006_4108h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 466: ...e crystal oscillator power mode of operations 0 Configure crystal oscillator for low gain operation 1 Configure crystal oscillator for high gain operation 2 EREFS External Reference Select Selects the...

Page 467: ...tions Field Description 31 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 SIRCSEL Slow IRC Selected 0 Slow IRC is not the system clock source 1 Slow...

Page 468: ...Slow IRC is enabled 19 3 12 Slow IRC Divide Register SCG_SIRCDIV To prevent glitches to the output divided clock change SIRDIV when the Slow IRC is disabled Address 4006_4000h base 204h offset 4006_42...

Page 469: ...ce 000 Output disabled 001 Divide by 1 010 Divide by 2 011 Divide by 4 100 Divide by 8 101 Divide by 16 110 Divide by 32 111 Divide by 64 19 3 13 Slow IRC Configuration Register SCG_SIRCCFG The SIRCCF...

Page 470: ...ck 8 MHz 19 3 14 Fast IRC Control Status Register SCG_FIRCCSR Address 4006_4000h base 300h offset 4006_4300h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FIRCERR FIRCSEL FIRCVLD LK 0 W w1c...

Page 471: ...is reserved This read only field is reserved and always has the value 0 9 FIRCTRUP Fast IRC Trim Update 0 Disable Fast IRC trimming updates 1 Enable Fast IRC trimming updates 8 FIRCTREN Fast IRC Trim...

Page 472: ...eld is reserved and always has the value 0 18 16 Reserved This field is reserved This bit field is reserved Software should write 0 to this bit field to maintain compatibility 15 11 Reserved This fiel...

Page 473: ...ffset 4006_4308h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RANGE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 474: ...0 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 TRIMDIV Fast IRC Trim Predivide Divide the System OSC down for Fast IRC trimming 000 Divide by...

Page 475: ...alue 0 15 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 8 TRIMCOAR Trim Coarse TRIMCOAR bits are used to coursely trim the Fast IRC Clock to within...

Page 476: ...n Chip POR only software can also clear this flag by writing a logic one NOTE The LOL Flag is set when the PLL reference is out of range Dunl in datasheet and is constantly modulated such that 3 conse...

Page 477: ...ot be written 22 18 Reserved This field is reserved This read only field is reserved and always has the value 0 17 SPLLCMRE System PLL Clock Monitor Reset Enable 0 Clock Monitor generates interrupt wh...

Page 478: ...eld to maintain compatibility 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 SPLLDIV2 System PLL Clock Divide 2 Clock divider 2 for System PLL U...

Page 479: ...is the clock source selected from the SOURCE bitfield of this register Address 4006_4000h base 608h offset 4006_4608h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MULT W Reset 0 0 0 0 0 0 0...

Page 480: ...46 00111 23 01111 31 10111 39 11111 47 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 PREDIV PLL Reference Clock Divider Selects the amount to d...

Page 481: ...rted on this device Reset SIRC RUN Valid SCG Modes HSRUN Valid SCG Modes SIRC FIRC VLPRUN Valid SCG Modes SYS PLL SYS PLL SOSC SOSC FIRC SIRC SOSC Run Run High Speed Run Very Low Power SCG Valid Mode...

Page 482: ...n SOSC mode SCGCLKOUT and system clocks are derived from the external System Oscillator Clock SOSC Information regarding SOSC operation during normal and low power stop modes is found in the Stop row...

Page 483: ...ocks to a multiplication factor as specified by its corresponding SCG_SPLLCFG MULT times the selected PLL reference frequency The PLL s programmable reference divider must be configured to produce a v...

Page 484: ...or Low Power Stop modes VLPS SPLLCLK is available in Normal Stop mode when all the following conditions are true SPLLCSR SPLLEN 1 SPLLCSR SPLLSTEN 1 SPLLSTEN control bit has no affect in VLPS Power mo...

Page 485: ...Modes The key features of the RTC oscillator are as follows Supports 32 kHz crystals with very low power Consists of internal feed back resistor Automatic Gain Control AGC to optimize power consumpti...

Page 486: ...gnment section to find out which signals are actually connected to the external pins Table 20 1 RTC Signal Descriptions Signal Description I O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O 20...

Page 487: ...s The following section shows the memory map and explains the register OSC32 memory map Absolute address hex Register name Width in bits Access Reset value Section page 4006_0000 RTC Oscillator Contro...

Page 488: ...he block 1 RTC 32k oscillator is stable 4 ROSCEREFS RTC 32k Oscillator external reference clcok selection NOTE If RTC_CR OSCE is set this bit will be bypassed OSC32 then works in crystal mode 0 Bypass...

Page 489: ...no reset state associated with the RTC oscillator 20 7 Interrupts The RTC oscillator does not generate any interrupts Chapter 20 RTC Oscillator OSC32 Kinetis KE1xF Sub Family Reference Manual Rev 4 06...

Page 490: ...Interrupts Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 490 NXP Semiconductors...

Page 491: ...RCDIV1 or DIV2 of fast IRC clock SCGFIRCLK SPLLDIV1_CLK SPLLDIV2_CLK SPLLDIV1 or DIV2 of PLL clock SCGPLLCLK 21 2 Introduction The Peripheral Clock Control module PCC provides peripheral clock control...

Page 492: ...dule External Peripheral Specific Clock Source This clock is used by the Peripheral Functional Logic example derive baud rates Clock Divide Control PCD bits in the Peripheral s PCC register Post Divid...

Page 493: ...cked and result in a bus error Read accesses are allowed and do not cause a bus error but may return different results from different cores on a mulit core SOC 21 4 1 PCC Register Descriptions 21 4 1...

Page 494: ...RTB PCC_PORTB 32 RW 80000000h 4006512Ch PCC PORTC PCC_PORTC 32 RW 80000000h 40065130h PCC PORTD PCC_PORTD 32 RW 80000000h 40065134h PCC PORTE PCC_PORTE 32 RW 80000000h 40065158h PCC PWT PCC_PWT 32 RW...

Page 495: ...or the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used...

Page 496: ...e peripheral is present on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock en...

Page 497: ...SH 40065080h PCC Register 21 4 1 4 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11...

Page 498: ...configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and...

Page 499: ...l 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software cannot...

Page 500: ...evice 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control...

Page 501: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserv...

Page 502: ...8 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has the...

Page 503: ...sed 0b Peripheral is not being used 1b Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 P...

Page 504: ...erved W Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 4 1 9 3 Fields Field Function 31 PR En...

Page 505: ...ritten when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000b Clock is off 001b System Oscillator Bus Clock 010b Slow IRC Clock 011b Fast IRC Clock 100b Reser...

Page 506: ...ing used 0b Peripheral is not being used 1b Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26...

Page 507: ...erved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 4 1 11 3 Fields Field Function 31 PR E...

Page 508: ...ly be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000b Clock is off 001b System Oscillator Bus Clock 010b Slow IRC Clock 011b Fast IRC Clock 100...

Page 509: ...al 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software canno...

Page 510: ...evice 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control...

Page 511: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reser...

Page 512: ...ion 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has...

Page 513: ...al 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software canno...

Page 514: ...present on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE C...

Page 515: ...the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 21 4 1 17 PCC FLEXTMR0 PCC_FLEXTMR0 21 4 1 17 1 Addre...

Page 516: ...24 PCS Peripheral Clock Source Select This read write bit field is used for peripherals that support various clock selections This field can only be written when the CGC bit is 0 clock disabled Likew...

Page 517: ...the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral i...

Page 518: ...ield is reserved and always has the value 0 21 4 1 19 PCC FLEXTMR2 PCC_FLEXTMR2 21 4 1 19 1 Address Register Offset PCC_FLEXTMR2 400650E8h PCC Register 21 4 1 19 2 Diagram Bits 31 30 29 28 27 26 25 24...

Page 519: ...rce Select This read write bit field is used for peripherals that support various clock selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set...

Page 520: ...Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This re...

Page 521: ...1 21 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved PCS Reserved W Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved...

Page 522: ...at support various clock selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000b Clock is off 001b System Oscillator...

Page 523: ...al 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software canno...

Page 524: ...device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Contr...

Page 525: ...Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Rese...

Page 526: ...support various clock selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000b Clock is off 001b System Oscillator Bus...

Page 527: ...al 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software canno...

Page 528: ...s device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Cont...

Page 529: ...s 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Res...

Page 530: ...n 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has t...

Page 531: ...al 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software canno...

Page 532: ...s device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Cont...

Page 533: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserv...

Page 534: ...28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has th...

Page 535: ...Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Peripheral Clock Source Select NOTE...

Page 536: ...PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 4 1...

Page 537: ...only bit field is reserved and always has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 21 4 1 33 P...

Page 538: ...sed Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value...

Page 539: ...used 0b Peripheral is not being used 1b Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24...

Page 540: ...Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 4 1 35 3 Fields Field Function 31...

Page 541: ...tten when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000b Clock is off 001b System Oscillator Bus Clock 010b Slow IRC Clock 011b Fast IRC Clock 100b Reserve...

Page 542: ...ing used 0b Peripheral is not being used 1b Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26...

Page 543: ...served W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 4 1 37 3 Fields Field Function 31 PR...

Page 544: ...written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000b Clock is off 001b System Oscillator Bus Clock 010b Slow IRC Clock 011b Fast IRC Clock 100b Res...

Page 545: ...used 0b Peripheral is not being used 1b Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24...

Page 546: ...Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 4 1 39 3 Fields Field Function 31 P...

Page 547: ...always has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 21 4 1 40 PCC CMP1 PCC_CMP1 21 4 1 40 1 Add...

Page 548: ...g used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the va...

Page 549: ...al 0b Clock disabled 1b Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0b Peripheral is not being used 1b Peripheral is being used Software canno...

Page 550: ...Memory map and register definition Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 550 NXP Semiconductors...

Page 551: ...eset JTAG reset nTRST reset Each of the reset sources has an associated bit in the system reset status RCM_SRS register Besides immediate reset the RCM module also supports optional delays of the syst...

Page 552: ...2 1 Power on reset POR When power is initially applied to the MCU or when the supply voltage drops below the power on reset re arm voltage level VPOR the POR circuit causes a POR reset condition As th...

Page 553: ...wakes and resets the device from any mode During a pin reset RCM_SRS PIN is set The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock RCM_RPC RSTFLTSS RCM_RPC RSTFLTS...

Page 554: ...r Management Controller PMC chapter for more information For LVR related content see Low Voltage Reset LVR Operation 22 2 2 3 Watchdog timer WDOG The watchdog timer WDOG monitors the operation of the...

Page 555: ...enerates a software reset request This reset forces a system reset of all major components except for the debug module A software reset causes the RCM_SRS SW bit to set 22 2 2 8 Lockup reset LOCKUP Th...

Page 556: ...tes before flash memory initialization begins earlier than when the Chip Reset negates 22 2 3 4 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has compl...

Page 557: ...AP controller state machine without resetting the state of the debug modules The nTRST pin does not cause a system reset 22 2 5 3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ DP...

Page 558: ...set as shown in the following table Table 22 2 Flash Option Register FTFE_FOPT definition Bit Num Field Value Definition 7 BOOTSRC_SEL Boot Source Selection these bits select the boot sources if boot...

Page 559: ...PT External pin selects boot options 0 Force Boot from ROM with update if BOOTCFG0 asserted where BOOTCFG0 is the boot config function which is muxed with NMI pin The RESET pin should be enabled when...

Page 560: ...ow 4 Early in reset sequencing the NVM option byte is read and stored to the Flash Memory module s FOPT register 5 When Flash Initialization completes the RESET_b pin is released If RESET_b continues...

Page 561: ...hows the boot sequence VDD 2 6V VDD 1 5V and vdd_lv 0 7V release driving RESET pin end system reset IFR include FOPT load ftfx initialization complete release core hold 22 50us VDD POR LVR Clock Reset...

Page 562: ...Boot Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 562 NXP Semiconductors...

Page 563: ...P 53 41 33 LPUART 0 LPUART0_TX PTB1 2 54 42 34 LPUART0_RX PTB0 2 80 63 51 1 LPUART1_TX PTC7 2 81 64 52 LPUART1_RX PTC6 2 27 22 18 LPSPI 0 LPSPI0_PCS 1 PTB5 3 28 23 19 LPSPI0_SOU T PTB4 3 47 39 31 LPSP...

Page 564: ...the program residing in the on chip read only memory ROM of a Kinetis microcontroller device There is hardware logic in place at boot time that either starts execution of an embedded image available o...

Page 565: ...lly supports internal flash security including ability to mass erase or unlock security via the backdoor key Protection of RAM used by the bootloader while it is running Provides command to read prope...

Page 566: ...tloader uses ROM and RAM memory vectors 0x1C00_0000 noinit 0x1C00_00C0 text 0x1C00_010 C 0x1C00_4000 ROM use 0x1FFF_F800 Available not used by ROM 0x2000_0688 0x2000_1800 16 KB of ROM 8KB of RAM Figur...

Page 567: ...tedValue Expected CRC value for application CRC check If the bits are all set then Kinetis bootloader by default will not perform any CRC check 0x10 1 enabledPeripherals Bitfield of peripherals to ena...

Page 568: ...ader configuration data to be recognized as valid If tag field verification fails then the Kinetis Bootloader assumes that the flash is not initialized and uses a predefined default configuration all...

Page 569: ...ector fetches from the CPU are redirected to the ROM s vector table in ROM memory at offset 0x1C00_0000 This ensures that any exceptions will be handled by the ROM After the Kinetis Bootloader has sta...

Page 570: ...Ping packet received on LPUARTn No Was a Ping packet received on LPI2Cn Was a Ping packet received on FlexCANn Is Timeout check enabled and has Timeout occurred Shutdown all peripherals Jump to user a...

Page 571: ...peed mode should be enabled in BCA 23 3 5 Bootloader Entry Point API Tree To run the Kinetis Bootloader a user application simply calls the runBootloader function To get the address of the entry point...

Page 572: ...r NULL 23 3 6 Bootloader Protocol This section explains the general protocol for the packet transfers between the host and the Kinetis Bootloader The description includes the transfer of packets for d...

Page 573: ...from host Generic response command packet to host Command Host Target ACK Process command Response ACK Figure 23 3 Command with No Data Phase 23 3 6 2 Command with incoming data phase The protocol fo...

Page 574: ...her packets while it the host is waiting for the response to a command If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success then the data phase...

Page 575: ...peration 23 3 6 3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains Command packet from host ReadMemory Response command packet to host kCommandFlag_HasD...

Page 576: ...ove the data phase is really considered part of the response command The host may not send any further packets while it the host is waiting for the response to a command If the ReadMemory Response com...

Page 577: ...acketized NOTE The term target refers to the Kinetis Bootloader device There are 6 types of packets used in the device Ping packet Ping Response packet Framing packet Command packet Data packet Respon...

Page 578: ...ng Ping packet to determine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host starts sending...

Page 579: ...a packet type is used for synchronization between the host and target Table 23 8 Special Framing Packet Format Byte Value Parameter 0 0x5A start byte 1 0xAn packetType The Packet Type field specifies...

Page 580: ...t byte 0 byte 1 byte 2 byte 3 Table 23 11 Command Header Format Byte Command Header Field 0 Command or Response tag The command header is 4 bytes long with these fields 1 Flags 2 Reserved Should be 0x...

Page 581: ...or sending responses to GetProperty command only Flags Each command packet contains a Flag byte Only bit 0 of the flag byte is used If bit 0 of the flag byte is set to 1 then data packets will follow...

Page 582: ...quence The generic response packet contains the framing packet data and the command packet data with generic response tag 0xA0 and a list of parameters defined in the next section The parameter count...

Page 583: ...count set to 2 for the status code and the data byte count parameters shown below Table 23 16 ReadMemoryResponse Parameters Byte Parameter Descripton 0 3 Status code The status of the associated Read...

Page 584: ...23 17 Parameters for Execute Command Byte Command 0 3 Jump address 4 7 Argument word 8 11 Stack pointer address The Execute command has no data phase Response Before executing the Execute command the...

Page 585: ...eset command has no data phase Response The target Kinetis Bootloader will return a GenericResponse packet with status code set to kStatus_Success before resetting the chip 23 3 8 3 GetProperty comman...

Page 586: ...Byte Command 0 3 Property tag Host Target Process Command Generic Response ACK 0x5A A1 ACK 0x5A A1 0x5A A4 0C 00 07 7A A7 00 00 02 00 00 00 00 00 00 01 4B 0x5A A4 08 00 73 D4 07 00 00 01 01 00 00 00 G...

Page 587: ...ponseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b CurrentVersion 23 3 8 4 SetProperty command The SetProperty command is used to change or alter the...

Page 588: ...acketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A VerifyWrites prop...

Page 589: ...of the command packet The FlashEraseAll command requires no parameters Host Target Process Command ACK 0x5A A1 ACK 0x5A A1 0x5A A4 04 00 C4 2E 01 00 00 00 0x5A A4 0C 00 53 63 A0 00 04 02 00 00 00 00...

Page 590: ...nd will fail and return kStatus_FlashAlignmentError 0x101 If the region specified does not fit in the flash memory space the FlashEraseRegion command will fail and return kStatus_FlashAddressError 0x1...

Page 591: ...s Codes Status Code kStatus_Success 0x0 kStatus_MemoryRangeInvalid 0x10200 kStatus_FlashAlignmentError 0x101 kStatus_FlashAddressError 0x102 kStatus_FlashAccessError 0x103 kStatus_FlashProtectionViola...

Page 592: ...ount 0x00 The FlashEraseAllUnsecure command has no data phase Response The target Kinetis Bootloader will return a GenericResponse packet with status code either set to kStatus_Success for successful...

Page 593: ...quence for FlashSecurityDisable Command Table 23 31 FlashSecurityDisable Command Packet Format Example FlashSecurityDisable Parameter Value Framing packet start byte 0x5A packetType 0xA4 kFramingPacke...

Page 594: ...a FlashEraseAll FlashEraseRegion or FlashEraseAllUnsecure command Writing to flash requires the start address to be 4 byte aligned 1 0 00 The byte count will be rounded up to a multiple of 4 and the t...

Page 595: ...teMemory startAddress 0x20000400 byteCount 0x64 Process Command Process Data Process Data Figure 23 14 Protocol Sequence for WriteMemory Command Table 23 33 WriteMemory Command Packet Format Example W...

Page 596: ...ry command The ReadMemory command returns the contents of memory at the given address for a specified number of bytes This command can read any region of Flash memory SRAM_L and SRAM_U memory accessib...

Page 597: ...A A4 0C 00 1D 23 03 00 00 02 00 04 00 20 64 00 00 00 Final Generic Response 0x5A A4 0C 00 0E 23 A0 00 00 02 00 00 00 00 03 00 00 00 Figure 23 15 Command sequence for read memory ReadMemory Parameter V...

Page 598: ...ction timeout but before jumping to the application entry point 23 4 Kinetis Flash Driver API To simplify flash code development the Kinetis ROM Bootloader has flash driver APIs that user applications...

Page 599: ...I among different targets with ROM bootloader Table 23 35 Different versions of the flash driver Flash driver API version Supported targets V1 0 KL03Z4 KL43Z4 KL33Z4 KL27Z4 KL17Z4 V1 1 KL27Z644 KL17Z6...

Page 600: ...rgin uint32_t failedAddress uint32_t failedData status_t flash_get_property flash_config_t config flash_property_tag_t whichProperty uint32_t value if defined FLASH_API_TREE_1_0 defined FLASH_API_TREE...

Page 601: ...10 4 PFlashCallback Pointer to a callback function used to do extra operations during erasure for example service watchdog 14 4 PFlashAccessSegmentSize Size of FAC access segment 18 4 PFlashAccessSegm...

Page 602: ...acceleration RAM memory uint32_t DFlashBlockBase For FlexNVM device this is the base address of D Flash memory FlexNVM memory For non FlexNVM device this field is unused uint32_t DFlashTotalSize For F...

Page 603: ..._t data structure in memory to store driver runtime state key Key used to validate erase operation Must be set to 0x6B65666B Table 23 40 Possible status response Value Constants Description 4 kStatus_...

Page 604: ...nt mode security 107 kStatus_FLASH_EraseKeyError Key is incorrect 0 kStatus_Success This function has performed successfully Example status_t status FLASH_EraseAllUnsecure flashInstance kFLASH_ApiEras...

Page 605: ...eyError Key is incorrect 0 kStatus_Success This function has performed successfully Example status_t status FLASH_Erase flashInstance 0x800 1024 kFLASH_ApiEraseKey 23 4 5 5 FLASH_Program Programs the...

Page 606: ...region to be programmed is empty and is not protected 23 4 5 6 FLASH_GetSecurityState Retrieves the current flash security status including the security enabling state and the backdoor key enabling s...

Page 607: ...fig Pointer to flash_config_t data structure in memory to store driver runtime state backdoorKey Pointer to the user buffer containing the backdoor key Table 23 51 Possible status response Value Const...

Page 608: ...choice kFLASH_MarginValueNormal 0 kFLASH_MarginValueUser 1 kFLASH_MarginValueFactory 2 Table 23 53 Possible status response Value Constant Description 4 kStatus_InvalidArgument Config or backdoorKey p...

Page 609: ...0 kFLASH_MarginValueUser 1 kFLASH_MarginValueFactory 2 Table 23 55 Possible status response Value Constant Description 4 kStatus_InvalidArgument Config or backdoorKey pointers are NULL 101 kStatus_FLA...

Page 610: ...bytes not words or long words to be verified Must be word aligned ExpectedData Pointer to the expected data that is to be verified against Margin Read margin choice as follows kFLASH_MarginValueUser...

Page 611: ...flash property which includes base address sector size and other options Prototype status_t flash_get_property flash_driver_t driver flash_property_t whichProperty uint32_t value Table 23 58 Parameter...

Page 612: ...FLASH_PropertyPflashSectorSize propertyValue 23 4 5 12 FLASH_ProgramOnce Programs a certain Program Once Field with the expected data for a given IFR region as determined by the index and length For e...

Page 613: ...ield has already been programmed to a non FFFF value 4 The requested sector crosses a flash block boundary 115 kStatus_FLASH_CommandNotSupported This function is not supported 0 kStatus_Success This f...

Page 614: ...r Index or lengthInBytes is invalid 103 kStatus_FLASH_AddressError The following situation causes this response 1 Command is not available under current mode security 2 An invalid index is supplied 11...

Page 615: ...ignmentError Start lengthInBytes or option is invalid 103 kStatus_FLASH_AccessError The following situation causes this response 1 Command is not available under current mode security 2 An invalid ind...

Page 616: ...oggle 23 5 Peripherals Supported This section describes the peripherals supported by the Kinetis ROM Bootloader To use an interface for bootloader communications the peripheral must be enabled in the...

Page 617: ...ddress and the direction bit is set as write An outgoing packet is read by the host with a selected I2C slave address and the direction bit is set as read 0x00 will be sent as the response to host if...

Page 618: ...n supported length Yes payload data from target No Set payload length to maximum supported length No No Reached maximum Report a timeout Yes End No 2 bytes Read 1 byte from target 0x5A received 0xA4 r...

Page 619: ...eceived bytes should be ignored when host is sending out bytes to target Host starts reading bytes by sending 0x00s to target The byte 0x00 will be sent as response to host if target is under the foll...

Page 620: ...ads ping packet from target via SPI Fetch ACK No Yes No Next action No Process NAK Yes Report an error No Yes No maximum Report a timeout error Yes 0x5A received 0xA2 received 0xA1 received Send 0x00...

Page 621: ...the detection phase in order to comply with the autobaud detection algorithm After the bootloader detects the ping packet 0x5A 0xA6 on UARTn_RX the bootloader firmware executes the autobaud sequence I...

Page 622: ...ion succeeds bootloader communications can take place over the UART peripheral The following flow charts show How the host detects an ACK from the target How the host detects a ping response from the...

Page 623: ...from target No Set payload length to maximum supported length No No Reached maximum Report a timeout error End Yes End No 0x5A received 0xA4 received Wait for 1 byte from target Wait for 1 byte from t...

Page 624: ...ge the speed setting and check again If there is no error which means the speed should be correct now it changes the settings back to normal receiving mode to see if there is a package for this node I...

Page 625: ...eads a command response from target via FlexCAN 23 6 Get SetProperty Command Properties This section lists the properties of the GetProperty and SetProperty commands Chapter 23 Kinetis ROM Bootloader...

Page 626: ...ndicates the number of pairs If HasDataPhase flag is set then the second parameter is the number of bytes in the data phase ValidateRegions Yes 0Dh 4 Controls whether the bootloader will validate atte...

Page 627: ...a 4 byte structure containing the current version of the bootloader Table 23 70 Fields of CurrentVersion property Bits 31 24 23 16 15 8 7 0 Field Name K 0x4B Major version Minor version Bugfix version...

Page 628: ...Reserved Reserved FlashEraseAllUnsecure SetProperty Reset Reserved Execute Reserved GetProperty FlashSecurityDisable Reserved WriteMemory ReadMemory FlashEraseRegion FlashEraseAll 23 7 Verifying the a...

Page 629: ...be asserted to indicate CRC check failure The bootloader will only jump to the application if kStatus_AppCrcCheckPassed is returned if kStatus_AppCrcCheckPassed is not returned then the bootloader wil...

Page 630: ...nProgress 304 Attempt to abort a transfer when no transfer was in progress kStatus_UnknownCommand 10000 The requested command value is undefined kStatus_SecurityViolation 10001 Command is disallowed b...

Page 631: ...t on this device NOTE High Voltage Detect HVD is not supported on this device Therefore HVD related descriptions are not applicable in RCM_SRS LVD NOTE In the RCM_SRIE register bit 8 JTAG and bit 11 M...

Page 632: ...SRS 32 R 0000_0082h 24 3 3 636 4007_F00C Reset Pin Control register RCM_RPC 32 R W 0000_0000h 24 3 4 639 4007_F010 Mode Register RCM_MR 32 R W See section 24 3 5 640 4007_F014 Force Mode Register RCM_...

Page 633: ...6 MINOR Minor Version Number This read only field returns the minor version number for the specification FEATURE Feature Specification Number This read only field returns the feature set number 0x0003...

Page 634: ...d ESW ELOCKUP Reserved EPOR EPIN EWDOG Reserved ELOL ELOC ELVD Reserved W Reset 0 0 1 0 0 1 1 0 1 1 1 0 1 1 1 1 RCM_PARAM field descriptions Field Description 31 17 Reserved This field is reserved Thi...

Page 635: ...tence of SRS LOCKUP status indication feature This static bit states whether or not the feature is available on the device 0 The feature is not available 1 The feature is available 8 Reserved This fie...

Page 636: ...whether or not the feature is available on the device 0 The feature is not available 1 The feature is available 0 Reserved This field is reserved 24 3 3 System Reset Status Register RCM_SRS This regis...

Page 637: ...reserved and always has the value 0 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 SACKERR Stop Acknowledge Error Indicates that after an attempt to...

Page 638: ...t not caused by JTAG 1 Reset caused by JTAG 7 POR Power On Reset Indicates a reset has been caused by the power on detection logic Because the internal supply voltage was ramping up at the time the lo...

Page 639: ...upply rises above the HVD trip voltage an HVD reset occurs This field is also set by POR 0 Reset not caused by LVD trip HVD trip or POR 1 Reset caused by LVD trip HVD trip or POR 0 Reserved This field...

Page 640: ...ring disabled 1 LPO clock filter enabled RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is enabled in run and wait modes 00 All filtering disabled 01 Bus cloc...

Page 641: ...iguration 0 Reserved This field is reserved This read only field is reserved and always has the value 0 24 3 6 Force Mode Register RCM_FM NOTE The reset values of the bits in the FORCEROM field are fo...

Page 642: ...hat have not been cleared by software Software can clear the status flags by writing a logic one to a flag Address 4007_F000h base 18h offset 4007_F018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 643: ...trol Register 0 Reset was not caused by host debugger system setting of the System Reset Request bit 1 Reset was caused by host debugger system setting of the System Reset Request bit 10 SSW Sticky So...

Page 644: ...t has been caused by a loss of external clock The SCG SOSC clock monitor must be enabled for a loss of clock to be detected Refer to the detailed SCG description for information on enabling the clock...

Page 645: ...ways has the value 0 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 Reserved This field is reserved This read only field is reserved and always has t...

Page 646: ...by external reset pin 5 WDOG Watchdog Interrupt 0 Interrupt disabled 1 Interrupt enabled 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 LOL Loss of Loc...

Page 647: ...les in these modes Following stated are general power modes which are supported additionally by certain clocking mode options Clock gating technique is used for general power modes and for the additio...

Page 648: ...n Default mode out of reset on chip voltage regulator is on Run High Speed Run Allows maximum performance of chip In this state the MCU is able to operate at a faster frequency compared to normal run...

Page 649: ...he MCU digital modules to operate at a normal frequency Very Low Power RUN mode The on chip regulator voltage is in Low Power mode The MCU digital modules should operate at a limited frequency but wit...

Page 650: ...tion including the MCM System Control Space SCS for NVIC and SysTick Although access to the GPIO registers is supported the GPIO port data input registers do not return valid data since clocks are dis...

Page 651: ...nstruction VLPW mode is entered when MCU is in VLPR mode and Normal Wait mode is entered when MCU is in Normal Run mode Run mode configurations can be selected by configuring SMC_PMCTRL Clock gating c...

Page 652: ...AWIC interrupt can be used as a wake up source from Stop normal Stop and VLPS mode See Table 25 5 for all the available wake up source Besides waking up the CPU from Stop mode the DMA can perform data...

Page 653: ...request asserts during the stop mode entry sequence or reentry if the request asserts during a DMA wakeup and can cause the SMC to assert its Stop Abort flag Once the DMA wake up completes entry into...

Page 654: ...4 Core TRGMUXx SRAM EWM SCG WDOG PCC CRC AXBS Lite FlexIO Boot ROM LPI2Cx SIM LPSPIx RCM LPUARTx MCM LPITx AIPS Lite FTMx AWIC PDBx eDMA LPTMRx DMAMUX RTC FlexCAN PORTx 25 2 5 Entering and exiting pow...

Page 655: ...the normal run state In run wait and stop modes active power regulation is enabled The VLPx modes offer a lower power operating mode than normal modes VLPR and VLPW are limited in frequency WAIT STOP...

Page 656: ...ock sources and or the internal supplies driven from the on chip regulator as defined for the targeted low power mode In wait modes most of the system clocks are not affected by the low power mode ent...

Page 657: ...lator low power low power low power low power LVD LVR disabled LVR active only disabled LVR active only disabled LVR active only disabled LVR active only POR Brown out Detection FF FF FF FF DMA FF Asy...

Page 658: ...c operation FF in PSTOP2 Async operation CAN FF wakeup in CPO FF wakeup FF in PSTOP2 wakeup Security CRC FF static in CPO FF static FF in PSTOP2 static Timers FTM FF static in CPO FF static static LPI...

Page 659: ...clock frequencies should be set to desired values for the modules working in 1 2 V power domain see Table 25 2 e g Boot ROM FlexIO LPIT LPTMR and communication modules 25 5 1 Peripheral doze Several...

Page 660: ...in interrupt is capable of waking the system ADC ADC is optional functional with clock source from SIRC or OSC CMP Functional in Stop VLPS modes with clock source from SIRC or OSC DAC Functional in VL...

Page 661: ...T pin low until VDD increases above VLVD During power on the POR keeps the device under reset until the supply voltage VDD reaches the specified threshold When VDD is above the threshold the device re...

Page 662: ...Power supply supervisor Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 662 NXP Semiconductors...

Page 663: ...SMC is responsible for sequencing the system into and out of all low power Stop and Run modes Specifically it monitors events to trigger transitions between power modes while controlling the power clo...

Page 664: ...n wait and stop modes Stop mode regulation is used during all very low power and low leakage modes During stop mode regulation the bus frequencies are limited in the very low power modes The SMC provi...

Page 665: ...continue to operate although their maximum frequency is restricted See the Power Management chapter for details on the maximum allowable frequencies VLPS The core clock is gated off System clocks to o...

Page 666: ...Register SMC_VERID Address 4007_E000h base 0h offset 4007_E000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAJOR MINOR FEATURE W Reset 0 0 0 0 0 0 0 1...

Page 667: ...d and always has the value 0 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 EVLLS0 Existence of VLLS0 feature This static bit states whether or not the...

Page 668: ...ing of the low power run or stop mode occurs by configuring the Power Mode Control register PMCTRL The PMPROT register can be written only once after any system reset If the MCU is configured for a di...

Page 669: ...ed 1 VLPR VLPW and VLPS are allowed 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 Reserved This field is reserved This read only field is reserved and...

Page 670: ...tion level has not been enabled using the PMPROT register NOTE RUNM may be set to VLPR only when PMSTAT RUN After being written to VLPR RUNM should not be written back to RUN until PMSTAT VLPR NOTE RU...

Page 671: ...are blocked if the protection level has not been enabled using the PMPROT register After any system reset this field is cleared by hardware on any successful write to the PMPROT register NOTE When set...

Page 672: ...r consumption In PSTOP2 only system clocks are gated allowing peripherals running on bus clock to remain fully functional In PSTOP1 both system and bus clocks are gated 00 STOP Normal Stop mode 01 PST...

Page 673: ...2 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PMSTAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SMC_PMSTAT field descriptions Field Description 31 8 Reserved This field is reserved This...

Page 674: ...ous figure Table 26 2 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Registe...

Page 675: ...ces exit back to RUN and does not allow a transition to VLPR 7 RUN VLPS PMPROT AVLP 1 PMCTRL STOPM 010 Sleep now or sleep on exit modes entered with SLEEPDEEP set which is controlled in System Control...

Page 676: ...Module Figure 26 2 Low power system components and connections 26 5 2 1 Stop mode entry sequence Entry into a low power stop mode Stop VLPS is initiated by a CPU executing the WFI instruction After t...

Page 677: ...SMC can abort the transition early and return to RUN mode without completely entering the stop mode An aborted entry is possible only if the interrupt occurs before the PMC begins the transition to st...

Page 678: ...frequency To further reduce power in this mode disable the clocks to unused modules using their corresponding clock gating control bits in the PCC s registers Before entering this mode the following...

Page 679: ...e Power Management chapter While in this mode the following restrictions must be adhered to The maximum allowable change in frequency of the system bus flash or core clocks is restricted to 2x double...

Page 680: ...stop regulation state In this state the regulator is designed to supply enough current to the device at a reduced frequency To further reduce power in this mode disable the clocks to unused modules VL...

Page 681: ...curs the CPU exits STOP mode and resumes processing beginning with the stacking operations leading to the interrupt service routine A system reset will cause an exit from STOP mode returning the devic...

Page 682: ...e in RUN WAIT VLPR or VLPW the mode controller drives a corresponding acknowledge for each signal that is both CDBGPWRUPACK and CSYSPWRUPACK When both requests are asserted the mode controller handles...

Page 683: ...ins the internal voltage regulator power on reset POR the low voltage reset LVR and the low voltage detect LVD systems 27 3 Features The PMC features include Internal voltage regulator offering a vari...

Page 684: ...voltage detect LVD circuit with two trip points VLVD and VLVW The LVD is disabled upon entering low power mode Two flags are available to indicate the status of the low voltage detect system The low v...

Page 685: ...VDIE 1 and PMC_LVDSC1 LVDRE 0 27 5 2 LVD Interrupt Operation By configuring the LVD circuit for interrupt operation LVDIE set PMC_LVDSC1 LVDF is set and an LVD interrupt request occurs upon detection...

Page 686: ...Voltage Detect Status and Control 2 Register PMC_LVDSC2 8 R W 00h 27 6 2 687 4007_D002 Regulator Status and Control Register PMC_REGSC 8 R W See section 27 6 3 688 4007_D004 Low Power Oscillator Trim...

Page 687: ...t Reset Enable This bit enables the low voltage detect events to generate a system reset 0 No system resets on low voltage detect events 1 If the supply voltage falls below VLVD a system reset will be...

Page 688: ...27 6 3 Regulator Status and Control Register PMC_REGSC This register contains general control and status bits for the regulator and the LPO Address 4007_D000h base 2h offset 4007_D002h Bit 7 6 5 4 3 2...

Page 689: ...or LPFLL if available on device are always disabled in LPM Note Using this bit it must be ensured that respective clock modules are disabled in STOP or VLPS mode Else severe malfunction of clock modul...

Page 690: ...7 6 5 4 3 2 1 0 Read 0 LPOTRIM Write Reset 0 0 0 POR 0 0 0 0 0 0 0 0 Notes LPOTRIM field After POR reset automatically loaded from Flash Memory IFR after Reset normal system reset PMC_LPOTRIM field de...

Page 691: ...is read only The SEC bit of FSEC byte controls the chip security status After enabling device security the debug port SWD cannot access the memory resources of the MCU and ROM boot loader also limited...

Page 692: ...o longer unsecure the MCU When backdoor key access is disabled FlashSecurityDisable command cannot be used Please refer to the ROM chapter for more details 28 2 2 Flash access protection FAC Flash acc...

Page 693: ...ram specific data into this field by FTFE Program Once command with index 0x00 0x07 The data can no longer be erased nor modified after programming The Program Once Field can be read through Read Once...

Page 694: ...On chip resource access control mechanism Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 694 NXP Semiconductors...

Page 695: ...ounter must not occur if the software code works well and services the watchdog to re start the actual counter The EWM differs from the internal watchdog in that it does not reset the MCU s CPU and pe...

Page 696: ...rough a reset the EWM remains disabled On exit from stop mode by an interrupt the EWM is re enabled and the counter continues to be clocked from the same value prior to entry to stop mode Note the fol...

Page 697: ...ock Divider Logic LPO_CLK Low Power Clock Clock Gating Cell AND Enable EWM_CTRL EWMEN EWM_CLKPRESCALER CLK_DIV 8 bit Counter OR Counter Value Reset to Counter EWM Refresh And EWM_out Output Control Me...

Page 698: ...Control Register EWM_CTRL 8 R W 00h 29 3 1 698 4006_1001 Service Register EWM_SERV 8 W always reads 0 00h 29 3 2 699 4006_1002 Compare Low Register EWM_CMPL 8 R W 00h 29 3 3 699 4006_1003 Compare Hig...

Page 699: ...e Register EWM_SERV The SERV register provides the interface from the CPU to the EWM module It is write only and reads of this register return zero Address 4006_1000h base 1h offset 4006_1001h Bit 7 6...

Page 700: ...locks time for the CPU to refresh the EWM counter NOTE This register can be written only once after a CPU reset Writing this register more than once generates a bus transfer error NOTE The valid value...

Page 701: ...elected low power clock source for running the EWM counter can be prescaled as below Prescaled clock frequency low power clock source frequency 1 CLK_DIV 29 4 Functional Description The following sect...

Page 702: ...the EWM_out signal only after the EWM is enabled by the EWMEN bit in the CTRL register Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset 29 4 2 Th...

Page 703: ...t accessible to the CPU 29 4 4 EWM Compare Registers The compare registers CMPL and CMPH are write once after a CPU reset and cannot be modified until another CPU reset occurs The EWM compare register...

Page 704: ...ut signal is asserted irrespective of the input EWM_in 29 4 6 EWM Interrupt When EWM_out is asserted an interrupt request is generated to indicate the assertion of the EWM reset out signal This interr...

Page 705: ...f the EWM module It enables EWM_in pin input with assert state logic zero enables interrupt when EWM_out is assert The compare value is also set into CMPL H register before enabling EWM Initialize the...

Page 706: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 706 NXP Semiconductors...

Page 707: ...his module Peripheral Clocking WDOG PCC module SOSC SIRC SCG module SCG DIVBUS SOSC_CLK SIRC_CLK WDOG module BUS_CLK LPO_CLK WDOG_CS CLK Peripheral Interface Clock 00 01 10 11 Registers 30 1 2 WDOG lo...

Page 708: ...e inputs independent from the bus clock Bus clock slow clock LPO clock from PMC SIRC 8 MHz IRC from SCG ERCLK external reference clock from SCG Programmable timeout period Programmable 16 bit timeout...

Page 709: ...ndow 30 2 2 Block diagram The following figure shows a block diagram of the WDOG module MUX MUX MUX ERCLK SIRC UPDATE EN CLK PRES WIN INT BUS_CLK 256 16 bit Window Register 0xD928 0xC520 Control Statu...

Page 710: ...dog Control and Status Register NOTE TST is cleared 0 0 on POR only Any other reset does not affect the value of this field Address 4005_2000h base 0h offset 4005_2000h Bit 31 30 29 28 27 26 25 24 23...

Page 711: ...56 pre scaling of watchdog counter reference clock The block diagram shows this clock divider option 0 256 prescaler disabled 1 256 prescaler enabled 11 ULK Unlock status This read only bit indicates...

Page 712: ...ounter to demonstrate that the watchdog is functioning properly See the Fast testing of the watchdog section This write once field is cleared 0 0 on POR only Any other reset does not affect the value...

Page 713: ...base 4h offset 4005_2004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CNTHIGH CNTLOW W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 714: ...the watchdog window register When window mode is enabled CS WIN is set The WIN register determines the earliest time that a refresh sequence is considered valid See the Watchdog refresh mechanism sec...

Page 715: ...rce independent of the bus clock for applications that need to meet more robust safety requirements Using a clock source other than the bus clock ensures that the watchdog counter continues to run if...

Page 716: ...the configuration time period 128 bus clocks ends This delay ensures a smooth transition before restarting the counter with the new configuration 30 4 2 Watchdog refresh mechanism The watchdog resets...

Page 717: ...early When Window mode is enabled the watchdog must be refreshed after the counter has reached a minimum expected time value otherwise the watchdog resets the MCU The minimum expected time value is s...

Page 718: ...its and ensuring that CS UPDATE is also set to 0 This provides a robust mechanism to configure the watchdog and ensure that a runaway condition cannot mistakenly disable or modify the watchdog configu...

Page 719: ...nabled CS INT 1 After a reset triggering event like a counter timeout or invalid refresh attempt the watchdog first generates an interrupt request Next the watchdog delays 128 bus clocks from the inte...

Page 720: ...it run to the overflow value takes a relatively long time 64 kHz clocks To help minimize the startup delay for application code after reset the watchdog has a feature to test the watchdog more quickly...

Page 721: ...and compare functions work for the selected byte Repeat the procedure selecting the other byte in step 2 NOTE CS TST is cleared by a POR only and not affected by other resets 30 4 7 2 Entering user m...

Page 722: ...an be configured once by set the WDOG_CS UPDATE 0 After that the watchdog cannot be reconfigured until a reset If set WDOG_CS UPDATE 1 when configuring the watchdog the watchdog can be reconfigured wi...

Page 723: ...eshing the Watchdog To refresh the watchdog and reset the watchdog counter to zero a refresh sequence is required DisableInterrupts disable global interrupt WDOG_CNT 0xB480A602 refresh watchdog Enable...

Page 724: ...Application Information Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 724 NXP Semiconductors...

Page 725: ...it or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose input data or output data the CRC result bitwise or bytewise This option is required for cer...

Page 726: ...y CRC calculation in progress stops when the MCU enters a low power mode that disables the module clock It resumes after the clock is enabled or via the system reset for exiting the low power mode Clo...

Page 727: ...2 1 0 R HU HL LU LL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_DATA field descriptions Field Description 31 24 HU CRC High Upper Byte In 16 bit CRC mode CTRL TCRC is...

Page 728: ...nal Half word Writable and readable in 32 bit CRC mode CTRL TCRC is 1 This field is not writable in 16 bit CRC mode CTRL TCRC is 0 LOW Low Polynominal Half word Writable and readable in both 32 bit an...

Page 729: ...transposed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FXOR Complement Read Of CRC Data Register Some CRC protocols require the final checksum to...

Page 730: ...o compute a 16 bit CRC 1 Clear CRC_CTRL TCRC to enable 16 bit CRC mode 2 Program the transpose and complement options in the CTRL register as required for the CRC calculation See Transpose feature and...

Page 731: ...C result complement for details 31 3 3 Transpose feature By default the transpose feature is not enabled However some CRC standards require the input data and or the final checksum to be transposed Th...

Page 732: ...Transpose type 01 3 CTRL TOT or CTRL TOTR is 10 Both bits in bytes and bytes are transposed reg 31 0 becomes reg 0 7 reg 8 15 reg 16 23 reg 24 31 31 31 0 0 Figure 31 3 Transpose type 10 4 CTRL TOT or...

Page 733: ...complement When CTRL FXOR is set the checksum is complemented The CRC result complement function outputs the complement of the checksum value stored in the CRC data register every time the CRC data r...

Page 734: ...L CRC_CTRL_TOT 3 CRC_CTRL_TOTR 0 CRC_CTRL_FXOR 1 CRC_CTRL_TCRC 1 CRC_CTRL_WAS 0 write polynomial register CRC_GPOLY 0x04c11bd7 write pre computed control register value along with WAS to start checksu...

Page 735: ...RL CRC_CTRL_WAS 1 write seed initial checksum CRC_DATA 0 deassert WAS by writing pre computed CRC control register value CRC_CTRL CRC_CTRL_WAS 1 write data dataSize sizeof data 8 bit reads and writes...

Page 736: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 736 NXP Semiconductors...

Page 737: ...e pinout and other available resources Several debug interfaces are supported IEEE 1149 1 JTAG Serial Wire Debug SWD ARM Real Time Trace Interface 1 pin asynchronous mode only The basic Cortex M4 debu...

Page 738: ...C system memory maps MDM AP Provides centralized control and status registers for an external debugger to control the device ROM Table Identifies which debug IP is available Core Debug Singlestep Regi...

Page 739: ...oreSight Architecture Specification 32 2 CM4 ROM table The ROM table is used to hold the information about the debug components The CM4 ROM table resides on the CM4 AHB AP and has entries for CM4 debu...

Page 740: ...igure TCK JTAGC TMS TDI TDO JTAG DP TCK TMS TDI TDO 1 0 SWD DP DBGCLK DBGDI DBGDOEN SWD JTAG SWITCHER TCK JTAG mode DBGDO TDI TMS Arm JTAG DP instruction loaded TDO Figure 32 2 Modified Debug Port The...

Page 741: ...l up JTAG_TCLK SWD_CLK I JTAG Test Clock I Serial Wire Clock Pull down JTAG_TDI I JTAG Test Data Input Pull up JTAG_TDO TRACE_SWO O JTAG Test Data Output O Trace output over a single pin N C JTAG_TRST...

Page 742: ...uctions Reserved 1 All other opcodes Decoded to select bypass register 1 The manufacturer reserves the right to change the decoding of reserved instruction codes in the future 32 6 JTAG status and con...

Page 743: ...0xF selects the bank with IDR A 3 2 2 b11 selects the IDR Register IDR register reads 0x001C_0000 Bus Matrix S eeControl and StatusRegister Descriptions Data 31 0 A 7 4 A 3 2 RnW APSEL Decode Debug P...

Page 744: ...e Core from reset and CPU operation begins 5 7 Reserved N 8 Timestamp Disable N Set this bit to disable the 48 bit global trace timestamp counter during debug halt mode when the core is halted 0 The t...

Page 745: ...in which Run to VLPS is attempted Per debug definition the system actually enters the Stop state A debugger should interpret deep sleep indication with SLEEPDEEP and SLEEPING asserted in conjuntion w...

Page 746: ...HB AP supported sideband signal called HABORT This signal is driven into the Bus Matrix which resets the Bus Matrix state so that AHB AP can access the Private Peripheral Bus for last ditch debugging...

Page 747: ...estamp The Cortex M4 clock or the bitclock rate of the Serial Wire Viewer SWV output clocks the counter 4 Global system timestamping Timestamps can optionally be generated using a system wide 48 bit c...

Page 748: ...ower mode exits and the system returns to a state with active debug In the case that the debugger logic is powered off the debugger is reset on recovery and must be reconfigured once the low power mod...

Page 749: ...AHB AP FF FF FF OFF ITM FF FF FF OFF TPIU FF FF FF OFF DWT FF FF FF OFF 32 14 Debug and Security When security is enabled FSEC SEC 10 the debug port capabilities are limited in order to prevent exploi...

Page 750: ...Debug and Security Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 750 NXP Semiconductors...

Page 751: ...block is communicated in serial format 33 1 1 Block diagram The following is a simplified block diagram of the JTAG Controller JTAGC block Refer to Register description for more information about the...

Page 752: ...1149 1 2001 defined test modes are supported as well as a bypass mode 33 1 3 1 Reset The JTAGC block is placed in reset when either power on reset is asserted or the TMS input is held high for enough...

Page 753: ...test mode is explained in more detail in JTAGC block instructions 33 1 3 3 Bypass mode When no test operation is required the BYPASS instruction can be loaded to place the JTAGC block into bypass mode...

Page 754: ...ption This section provides a detailed description of the JTAGC block registers accessible through the TAP interface including data registers and the instruction register Individual bit level descript...

Page 755: ...is always a logic 0 33 3 3 Device identification register The device identification JTAG ID register shown in the following figure allows the revision number part number manufacturer and design cente...

Page 756: ...ctive It is used to capture input pin data force fixed values on output pins and select a logic value and direction for bidirectional pins Each bit of the boundary scan register represents a separate...

Page 757: ...ntroller is a synchronous state machine that interprets the sequence of logical values on the TMS pin The following figure shows the machine s states The value shown next to each state is the value of...

Page 758: ...EXIT1 DR EXIT1 IR P AUSE DR P AUSE IR EXIT2 IR EXIT2 DR UPDA TE DR UPDA TE IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 4 IEEE 1149 1 2001 TAP controller finite state...

Page 759: ...9 1 2001 standard for more details All undefined opcodes are reserved Table 33 3 4 bit JTAG instructions Instruction Code 3 0 Instruction summary IDCODE 0000 Selects device identification register for...

Page 760: ...nstruction has two functions The SAMPLE portion of the instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cell...

Page 761: ...can register using the SAMPLE PRELOAD instruction before the selection of EXTEST EXTEST asserts the internal system reset for the MCU to force a predictable internal state while performing external bo...

Page 762: ...n The boundary scan register consists of this shift register chain and is connected between TDI and TDO when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are loaded The shift register chain contai...

Page 763: ...locations of these pins on the devices supported by this document The Port Control Module is responsible for selecting which ALT functionality is available on each pin NOTE On this device there are s...

Page 764: ...VREFH VREFH VREFH 13 VREFL VREFL VREFL 14 VSS VSS VSS 15 11 PTB7 EXTAL EXTAL PTB7 LPI2C0_SCL 16 12 PTB6 XTAL XTAL PTB6 LPI2C0_SDA 17 PTE14 ACMP2_IN3 ACMP2_IN3 PTE14 FTM0_FLT1 FTM2_FLT1 18 13 PTE3 DISA...

Page 765: ...45 29 PTC15 ADC0_SE13 ACMP2_IN4 ADC0_SE13 ACMP2_IN4 PTC15 FTM1_CH3 46 30 PTC14 ADC0_SE12 ACMP2_IN5 ADC0_SE12 ACMP2_IN5 PTC14 FTM1_CH2 47 31 PTB3 ADC0_SE7 ADC0_SE7 PTB3 FTM1_CH1 LPSPI0_SIN FTM1_QD_ PH...

Page 766: ...PTA1 ADC0_SE1 ACMP0_IN1 ADC0_SE1 ACMP0_IN1 PTA1 FTM1_CH1 LPI2C0_SDAS FXIO_D3 FTM1_QD_ PHA LPUART0_ RTS TRGMUX_ OUT0 79 50 PTA0 ADC0_SE0 ACMP0_IN0 ADC0_SE0 ACMP0_IN0 PTA0 FTM2_CH1 LPI2C0_SCLS FXIO_D2...

Page 767: ...ins via its module itself or the SIM module Please see the respective module chapter and Port control and interrupt module features for details 100 LQFP 64 LQFP Pin Name Driver strength Default status...

Page 768: ...Y 31 22 PTD7 ND Hi Z Y 32 23 PTD6 ND Hi Z Y 33 24 PTD5 ND Hi Z Y 34 PTD12 ND Hi Z Y 35 PTD11 ND Hi Z Y 36 PTD10 ND Hi Z Y 37 VSS 38 VDD 39 25 PTC1 ND Hi Z Y 40 26 PTC0 ND Hi Z Y 41 PTD9 ND Hi Z Y 42 P...

Page 769: ...H PU N Y 71 46 PTD2 ND Hi Z Y 72 47 PTA3 ND Hi Z Y 73 48 PTA2 ND Hi Z Y 74 PTB11 ND Hi Z Y 75 PTB10 ND Hi Z Y 76 PTB9 ND Hi Z Y 77 PTB8 ND Hi Z Y 78 49 PTA1 ND Hi Z Y 79 50 PTA0 ND Hi Z Y 80 51 PTC7...

Page 770: ...POR Hi Z High impendence H High level L Low level Pullup pulldown setting after POR PU Pullup PD Pulldown Slew rate after POR FS Fast slew rate SS Slow slew rate Passive Pin Filter after POR N Disabl...

Page 771: ...PTE9 PTD15 PTD16 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 PTA9 PTA0 PTA1 PTB8 PTB9 50 49 48 47 46 45 44 43 42 41 PTC12 PTC13 PTB2 PTB3 PTC14 PTC15 PTC16 PTC17 PTD8 PTD9 PTC0 PTC1 VD...

Page 772: ...2 PTA13 PTE2 PTE6 PTC6 PTC7 PTA0 PTA1 PTA2 PTA3 PTD2 PTD3 PTD4 PTB12 PTB13 VDD VSS PTE7 PTA6 PTA7 PTC8 PTC9 PTB0 PTB1 PTB2 PTB3 PTC14 PTC15 PTC16 PTC17 PTC0 PTC1 PTD5 PTD6 PTD7 PTC2 Figure 34 2 64 LQF...

Page 773: ...le 34 3 System Signal Descriptions Chip signal name Module signal name Description I O NMI_b Non maskable interrupt NOTE Driving the NMI signal low forces a non maskable interrupt if the NMI function...

Page 774: ...iptions Chip signal name Module signal name Description I O ADCn_SE 15 0 AD 15 0 Single Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select...

Page 775: ...input j where j can be 3 0 I TCLK 2 0 EXTCLK External clock FTM external clock can be selected to drive the FTM counter I 34 3 6 Communication Interfaces Table 34 13 CANn Signal Descriptions Chip sig...

Page 776: ...e data I LPUARTn_CTS LPUART_CTS Clear to send I LPUARTn_RTS LPUART_RTS Request to send O Table 34 17 FlexIO Signal Descriptions Chip signal name Module signal name Description I O FXIO_D 7 0 FXIO_D 7...

Page 777: ...LT7 out en ALT5 out en ALT6 out en MUX 0 1 2 3 4 5 6 7 PDO ALT2 out data ALT3 out data ALT4 out data ALT7 out data ALT5 out data ALT6 out data glitch filter VDD PE PS VDD 0 1 1 1 1 PFE SRE DSE ODE 0 1...

Page 778: ...No No No PTD3 Yes Others No No Passive filter enable at reset PTA5 Enabled Others Disabled Disabled Disabled Disabled Disabled Open drain enable control Disabled Disabled Disabled Disabled Disabled Op...

Page 779: ...support for port control digital filtering and external interrupt functions Most functions can be configured independently for each pin in the 32 bit port and affect the pin regardless of its pin muxi...

Page 780: ...ital pin muxing modes 35 3 2 Modes of operation 35 3 2 1 Run mode In Run mode the PORT operates normally 35 3 2 2 Wait mode In Wait mode PORT continues to operate normally and may be configured to exi...

Page 781: ...asynchronously to the system clock Negation may occur at any time and can assert asynchronously to the system clock 35 6 Memory map and register definition Any read or write access to the PORT memory...

Page 782: ...See section 35 6 1 788 4004_9050 Pin Control Register n PORTA_PCR20 32 R W See section 35 6 1 788 4004_9054 Pin Control Register n PORTA_PCR21 32 R W See section 35 6 1 788 4004_9058 Pin Control Regis...

Page 783: ...6 1 788 4004_A044 Pin Control Register n PORTB_PCR17 32 R W See section 35 6 1 788 4004_A048 Pin Control Register n PORTB_PCR18 32 R W See section 35 6 1 788 4004_A04C Pin Control Register n PORTB_PC...

Page 784: ...04_B038 Pin Control Register n PORTC_PCR14 32 R W See section 35 6 1 788 4004_B03C Pin Control Register n PORTC_PCR15 32 R W See section 35 6 1 788 4004_B040 Pin Control Register n PORTC_PCR16 32 R W...

Page 785: ...ection 35 6 1 788 4004_C030 Pin Control Register n PORTD_PCR12 32 R W See section 35 6 1 788 4004_C034 Pin Control Register n PORTD_PCR13 32 R W See section 35 6 1 788 4004_C038 Pin Control Register n...

Page 786: ..._D024 Pin Control Register n PORTE_PCR9 32 R W See section 35 6 1 788 4004_D028 Pin Control Register n PORTE_PCR10 32 R W See section 35 6 1 788 4004_D02C Pin Control Register n PORTE_PCR11 32 R W See...

Page 787: ...l Pin Control Low Register PORTE_GPCLR 32 W always reads 0 0000_0000h 35 6 2 791 4004_D084 Global Pin Control High Register PORTE_GPCHR 32 W always reads 0 0000_0000h 35 6 3 791 4004_D0A0 Interrupt St...

Page 788: ...0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LK 0 MUX 0 DSE Reserved PFE 0 Reserved PE PS W Reset 0 0 0 0 0 0 0 0 0 Notes MUX field Varies by port See Signal Multiplexing and Signal...

Page 789: ...d 0001 ISF flag and DMA request on rising edge 0010 ISF flag and DMA request on falling edge 0011 ISF flag and DMA request on either edge 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 I...

Page 790: ...n the corresponding pin 1 Passive input filter is enabled on the corresponding pin if the pin is configured as a digital input Refer to the device data sheet for filter characteristics 3 Reserved This...

Page 791: ...s bits 15 0 that are selected by GPWE 35 6 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25 24...

Page 792: ...the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a level sensitive interrupt and the pin remains asserted...

Page 793: ...is field is reserved This read only field is reserved and always has the value 0 0 CS Clock Source The digital filter configuration is valid in all digital pin muxing modes Configures the clock source...

Page 794: ...port pin It also includes a flag to indicate that an interrupt has occurred The lower half of the Pin Control register configures the following functions for each pin within the 32 bit port Pullup or...

Page 795: ...power consumption 35 7 2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins all with the same v...

Page 796: ...is detected This also generates an asynchronous wake up signal to exit the Low Power mode 35 7 4 Digital filter The digital filter capabilities of the PORT module are available in all digital Pin Muxi...

Page 797: ...the output of the digital filter updates to equal the synchronized filter input The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration regist...

Page 798: ...Functional description Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 798 NXP Semiconductors...

Page 799: ...tion and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function The GPIO input data register displays the logic value on each pin when...

Page 800: ...gnal descriptions GPIO signal descriptions Description I O PORTA31 PORTA0 General purpose input output I O PORTB31 PORTB0 General purpose input output I O PORTC31 PORTC0 General purpose input output I...

Page 801: ...GPIO ports available in the device 36 3 Memory map and register definition Any read or write access to the GPIO memory space that is outside the valid memory map results in a bus error GPIO memory ma...

Page 802: ...OC_PTOR 32 W always reads 0 0000_0000h 36 3 4 804 400F_F090 Port Data Input Register GPIOC_PDIR 32 R 0000_0000h 36 3 5 805 400F_F094 Port Data Direction Register GPIOC_PDDR 32 R W 0000_0000h 36 3 6 80...

Page 803: ...s 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PDO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDOR field des...

Page 804: ...s Field Description PTCO Port Clear Output Writing to this register will update the contents of the corresponding bit in the Port Data Output Register PDOR as follows 0 Corresponding bit in PDORn does...

Page 805: ...0 0 GPIOx_PDIR field descriptions Field Description PDI Port Data Input Reads 0 at the unimplemented pins for a particular device Pins that are not configured for a digital function read 0 If the Port...

Page 806: ...n when a port is not required for general purpose input functionality 36 4 2 General purpose output The logic state of each pin can be controlled via the port data output registers and port data direc...

Page 807: ...to be enabled to update the state of the port data direction registers and port data output registers including the set clear toggle registers Chapter 36 General Purpose Input Output GPIO Kinetis KE1x...

Page 808: ...Functional description Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 808 NXP Semiconductors...

Page 809: ...with packages as indicated in following table For details regarding a specific ADC channel available on a particular package refer to the signal multiplexing chapter of this MCU Table 37 1 ADC extern...

Page 810: ..._SE8 01001 AD9 PTC1 ADC0_SE9 01010 AD10 PTC2 ADC0_SE10 01011 AD11 PTC3 ADC0_SE11 01100 AD12 PTC14 ADC0_SE12 01101 AD13 PTC15 ADC0_SE13 01110 AD14 PTC16 ADC0_SE14 01111 AD15 PTC17 ADC0_SE15 10000 AD16...

Page 811: ...DC1_SE9 01010 AD10 PTE2 ADC1_SE10 01011 AD11 PTE6 ADC1_SE11 01100 AD12 PTA15 ADC1_SE12 01101 AD13 PTA16 ADC1_SE13 01110 AD14 PTB15 ADC1_SE14 01111 AD15 PTB16 ADC1_SE15 10000 AD16 Reserved 10001 AD17 R...

Page 812: ...ADC2_SE9 01010 AD10 PTB9 ADC2_SE10 01011 AD11 PTB8 ADC2_SE11 01100 AD12 PTE10 ADC2_SE12 01101 AD13 PTE11 ADC2_SE13 01110 AD14 PTC8 ADC2_SE14 01111 AD15 PTC9 ADC2_SE15 10000 AD16 Reserved 10001 AD17 R...

Page 813: ...CDIV2_CLK FIRCDIV2_CLK ADCx module BUS_CLK Peripheral Interface Clock PCC_ADCx PCS 00 01 10 11 see PCC chapter for detailed setting Registers NA ALTCLK1 ALTCLK2 ALTCLK3 ALTCLK4 NA NA NOTE ALTCLK2 4 ar...

Page 814: ...RG ADCx_COCOB_TRG TRIGGER PRE TRIGGER PDBx_ADCx_pretrig0 PDBx_ADCx_pretrig1 PDBx_ADCx_pretrig2 PDBx_ADCx_pretrig3 PDBx_ADCx_pretrig4 PDBx_ADCx_pretrig5 PDBx_ADCx_pretrig6 PDBx_ADCx_pretrig7 TRGMUX_ADC...

Page 815: ...d ADC1 The interleaved mode is enabled by SIM_CHIPCTL ADC_INTERLEAVE_EN bits The hardware interleave implementation on this device is as follows ADC0_SE4 and ADC1_SE14 channels are interleaved on PTB0...

Page 816: ...citors in the range 1 F 100 nF and 1 nF Capacitors should be placed to the VREFH pin as close as possible Bandgap from PMC connected as the VALT2 reference option The VALT2 input is also connected wit...

Page 817: ...ntrolled by software to determine relative priority It should not trigger the ADC again before a single conversion has not completed The following triggers are via the TRGMUX CMP out to trigger each A...

Page 818: ...DC0TRGSEL PDB triggering scheme PDB triggering scheme is the default and suggested trigger method for ADC One ADC and one PDB work as one pair the implementation on this device is PDB0 ADC0 PDB1 ADC1...

Page 819: ...X out is selected as ADC trigger source Configure TRGMUX to select LPIT triggers as ADC trigger and pre trigger source TRGMUX only supports up to 4 pre triggers for each ADC pre trigger0 pre trigger3...

Page 820: ...only support SC1A and data register A Configure SC2 ADTRG 1 ADC is in hardware triggering mode By setting SIM_ADCOPT ADCxSWPRETRG the pre trigger for ADC is selected The software trigger trough TRGMUX...

Page 821: ...ces Operation in low power modes for lower noise Selectable hardware conversion trigger with hardware channel select Automatic compare with interrupt for less than greater than or equal to within rang...

Page 822: ...DLSMP ADLSTS Control sequencer Clock divide ALTCLK2 SAR converter Offset subtractor Averager Formatting Compare logic initialize sample convert transfer abort V REFL BNGP VREFH VREFL ALTCLK3 TEMPSENSE...

Page 823: ...e same voltage potential as VSS 37 3 3 Voltage Reference Select VREFSH and VREFSL are the high and low reference voltages for the ADC module The ADC can be configured to accept one of the voltage refe...

Page 824: ..._001Fh 37 4 1 829 4002_700C ADC Status and Control Register 1 ADC1_SC1D 32 R W 0000_001Fh 37 4 1 829 4002_7010 ADC Status and Control Register 1 ADC1_SC1E 32 R W 0000_001Fh 37 4 1 829 4002_7014 ADC St...

Page 825: ...ADC1_CLP3 32 R W See section 37 4 16 842 4002_70BC ADC Plus Side General Calibration Value Register 2 ADC1_CLP2 32 R W See section 37 4 17 843 4002_70C0 ADC Plus Side General Calibration Value Regist...

Page 826: ...32 R 0000_0000h 37 4 4 833 4003_B058 ADC Data Result Registers ADC0_RE 32 R 0000_0000h 37 4 4 833 4003_B05C ADC Data Result Registers ADC0_RF 32 R 0000_0000h 37 4 4 833 4003_B060 ADC Data Result Regi...

Page 827: ...lue Register 9 ADC0_CLP9_OFS 32 R W 0000_0240h 37 4 28 848 4003_C000 ADC Status and Control Register 1 ADC2_SC1A 32 R W 0000_001Fh 37 4 1 829 4003_C004 ADC Status and Control Register 1 ADC2_SC1B 32 R...

Page 828: ...er 3 ADC2_CLP3 32 R W See section 37 4 16 842 4003_C0BC ADC Plus Side General Calibration Value Register 2 ADC2_CLP2 32 R W See section 37 4 17 843 4003_C0C0 ADC Plus Side General Calibration Value Re...

Page 829: ...A while SC1A is actively controlling a conversion aborts the current conversion In Software Trigger mode when SC2 ADTRG 0 writes to SC1A initiate a new conversion This is valid for all values of SC1A...

Page 830: ...letion of the selected number of conversions determined by AVGS if one or more of the following is true The hardware average function is enabled SC3 AVGE 1 COCO in SC1A is also set at the completion o...

Page 831: ...rnal channel 4 is selected as input 00101 Exernal channel 5 is selected as input 00110 Exernal channel 6 is selected as input 00111 Exernal channel 7 is selected as input 01000 Exernal channel 8 is se...

Page 832: ...ratio used by the ADC to generate the internal clock ADCK 00 The divide ratio is 1 and the clock rate is input clock 01 The divide ratio is 2 and the clock rate is input clock 2 10 The divide ratio i...

Page 833: ...lue 0 SMPLTS Sample Time Select Selects a sample time of 2 to 256 ADCK clock cycles The value written to this register field is the desired sample time minus 1 A sample time of 1 is not supported Allo...

Page 834: ...erved This field is reserved This read only field is reserved and always has the value 0 D Data result 37 4 5 Compare Value Registers ADCx_CVn The Compare Value Registers CV1 and CV2 contain a compare...

Page 835: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 ADACT ADTRG ACFE ACFGT ACREN DMAEN REFSEL W Reset 0 0 0 0 0 0...

Page 836: ...Function Greater Than Enable Configures the compare function to check the conversion result relative to CV1 and CV2 based upon the value of ACREN ACFE must be set for ACFGT to have any effect See Tab...

Page 837: ...writes to the ADC registers or the results will be invalid Setting CAL will abort any current conversion NOTE For calibration it is mandatory to use averaging and average number 32 NOTE If several AD...

Page 838: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ADCx_BASE_OFS field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the val...

Page 839: ...e value 0 OFS Offset Error Correction Value 37 4 10 USER Offset Correction Register ADCx_USR_OFS The ADC USER Offset Correction Register USR_OFS contains the user defined offset error correction value...

Page 840: ...et error correction value 37 4 12 ADC Y Offset Correction Register ADCx_YOFS The ADC Y Offset Correction Register YOFS contains the Y offset used in the conversion result error correction algorithm Ad...

Page 841: ...Address Base address B0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0...

Page 842: ...tion Value 37 4 16 ADC Plus Side General Calibration Value Register 3 ADCx_CLP3 Address Base address B8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 843: ...has the value 0 CLP2 Calibration Value 37 4 18 ADC Plus Side General Calibration Value Register 1 ADCx_CLP1 Address Base address C0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 844: ...CLP0 Calibration Value 37 4 20 ADC Plus Side General Calibration Value Register X ADCx_CLPX Address Base address C8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0...

Page 845: ...0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 Reserved CLP9 W Reset 0 0 0 0 0 0 0 0 0 Notes CLP9 field Reset values are loaded out of IFR ADCx_CLP9 field descriptions Field De...

Page 846: ...set Capacitor offset correction value 37 4 23 ADC Plus Side General Calibration Offset Value Register 3 ADCx_CLP3_OFS Address Base address D4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 847: ...offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLP1_OFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_CLP1_OFS fie...

Page 848: ...erved This field is reserved This read only field is reserved and always has the value 0 CLPX_OFS CLPX Offset Capacitor offset correction value 37 4 28 ADC Plus Side General Calibration Offset Value R...

Page 849: ...has been enabled or when SC1n AIEN 1 The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers The compare function is ena...

Page 850: ...lected using SC2 REFSEL The alternate VALTH voltage reference may select additional external pin or internal source depending on MCU configuration See the chip configuration information for the voltag...

Page 851: ...sion When the conversion is completed the result is placed in the Rn registers associated with the ADHWTSn received For example ADHWTSA active selects RA register ADHWTSn active selects Rn register Th...

Page 852: ...rsion In software triggered operation that is when SC2 ADTRG 0 continuous conversions begin after SC1A is written and continue until aborted In hardware triggered operation that is when SC2 ADTRG 1 an...

Page 853: ...trolling a conversion aborts the current conversion In Software Trigger mode when SC2 ADTRG 0 a write to SC1A initiates a new conversion if SC1A ADCH is equal to a value other than all 1s Writing to a...

Page 854: ...completion of the conversion algorithm The maximum total conversion time is determined by the clock source chosen and the divide ratio selected The clock source is selectable by CFG1 ADICLK and the d...

Page 855: ...sult falls within or outside a range determined by two compare values The compare mode is determined by SC2 ACFGT SC2 ACREN and the values in the Compare Value registers CV1 and CV2 After the input is...

Page 856: ...register Rn If the hardware averaging function is enabled the compare function compares the averaged result to the compare values The same compare function definitions apply An ADC interrupt is genera...

Page 857: ...n VDDA and VSSA Suggested cap sizes 1 nF 100 nF 10 F Place caps on PCB as close as possible to the device pins VDDA and VSSA Routing of VDDA VSSA VREFH and VREFL on PCB Low impedance between the bypas...

Page 858: ...de from which recovery is fast because the clock sources remain active If a conversion is in progress when the MCU enters Wait mode it continues until completion Conversions can be initiated while the...

Page 859: ...st completed conversion that occurred during Normal Stop mode If the hardware averaging function is enabled SC1n COCO will set and generate an interrupt if enabled when the selected number of conversi...

Page 860: ...ADLSMP 1 Configures for long sample time Bit 3 2 MODE 10 Selects the single ended 10 bit conversion Bit 1 0 ADICLK 00 Selects the bus clock ADC_SC2 0x00 Bit 7 ADACT 0 Flag indicates if a conversion is...

Page 861: ...than specified accuracy In order to calibrate ADC correctly the following steps have to be done On startup wait until reference voltage VREFH VREFL has stabilized use 3 bypass capacitance in the rang...

Page 862: ...6 5 DMA Support on ADC Applications may require continuous sampling of the ADC 4K samples sec that may have considerable load on the CPU Though using PDB to trigger ADC may reduce some CPU load the A...

Page 863: ...e ADC trigger is initiated after pre trigger to trigger ADC conversion The waveforms shown in following diagram illustrate the pre trigger and trigger output of PDB to ADC Every time when one PDB pre...

Page 864: ...Figure 37 5 PWM Load Diagnosis ADC Trigger Concept 1 Timing Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 864 NXP Semiconductors...

Page 865: ...ified accuracy Calibration must be run or valid calibration values written after any reset and before a conversion is initiated Not doing this can result in ADC conversion results with lower than spec...

Page 866: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 866 NXP Semiconductors...

Page 867: ...independently in STOP and VLPS mode whilst being triggered periodically to sample up to 7 inputs Only if an input changes state is a full wakeup generated 38 1 1 1 CMP input connections The following...

Page 868: ...SCG module SCG DIVBUS CMPn module BUS_CLK Peripheral Interface Clock Registers Main Clock internal 38 1 3 Inter connectivity Information The CMP inter connectivity is shown in following diagram Chip s...

Page 869: ...AC sub block supports selection of two references For this device the references are connected as follows VDDA connected to Vin1 of CMP PMC bandgap buffer out 1V reference voltage connected to Vin2 of...

Page 870: ...e trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output In this device control for this two staged sequenci...

Page 871: ...signal input selects the output voltage level which varies from Vin to Vin 256 Vin can be selected from two voltage sources Vin1 and Vin2 The DAC from a comparator is available as an on chip internal...

Page 872: ...r modes available on this MCU The window and filter functions are not available in STOP modes The comparator can be triggered by other peripherals to work for only a small fraction of the time 38 3 2...

Page 873: ...Vin1 Vin2 Window and filter control CMPO Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INN Reference Input 7 INPSEL...

Page 874: ...ck CMPO To other SOC functions Internal bus Figure 38 2 Comparator module block diagram In the CMP block diagram The Window Control block is bypassed when C0 WE 0 If C0 WE 1 the comparator output is s...

Page 875: ...section provides the comparator pin descriptions The external inputs IN 7 0 are muxed by CMP_C1 PSEL and CMP_C1 MSEL beforehand and multiplexed output will then go to the second stage of multiplex wit...

Page 876: ...the simplest case only one sample must agree In this case the filter acts as a simple sampler The external sample input is enabled using C0 SE When set the output of the comparator is sampled only on...

Page 877: ...l determined by C0 FPR to generate COUT See the Windowed Resampled mode 6 7 1 1 0 0x01 0x01 0xFF Windowed Filtered mode Comparator output is sampled on every rising bus clock edge when SAMPLE 1 to gen...

Page 878: ...tion in Continuous mode NOTE See the chip configuration section for the source of sample window input The analog comparator block is powered and active CMPO may be optionally inverted but is not subje...

Page 879: ...powered and active The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block clo...

Page 880: ...figure illustrates comparator operation in this mode assuming the polarity select is set to non inverting state Sample Point CMPO COUT Figure 38 7 Sampled Non Filtered Mode Timing Diagram 38 7 4 Samp...

Page 881: ...1 WE 0 SE 1 CGMUX COS 1 0 FILT_PER bus clock COS IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt contr...

Page 882: ...t now C0 FILTER_CNT 1 which activates filter operation 38 7 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analog comparator...

Page 883: ...dow control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 38 11 Windowed mode For control configurations which result in disabling th...

Page 884: ...upon the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully considered for a given ap...

Page 885: ...clocked by the bus clock whenever WINDOW 1 The last latched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS 0 1...

Page 886: ...0_C2 32 R W 0000_0000h 38 8 3 893 4007_4000 CMP Control Register 0 CMP1_C0 32 R W 0000_0000h 38 8 1 886 4007_4004 CMP Control Register 1 CMP1_C1 32 R W 0000_0000h 38 8 2 890 4007_4008 CMP Control Regi...

Page 887: ...0 DMAEN DMA Enable Enables the DMA transfer triggered from the CMP module When this field is set a DMA request is asserted when CFR or CFF is set 0 DMA is disabled 1 DMA is enabled 29 Reserved This fi...

Page 888: ...parator output filter when C0 SE 0 Setting FPR to 0x0 disables the filter Filter programming and latency details are provided in the CMP functional description This field has no effect when C0 SE 1 In...

Page 889: ...no power 0 Analog Comparator is disabled 1 Analog Comparator is enabled 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 4 FILTER_CNT Filter Sample Count...

Page 890: ...level 1 hysteresis internally 10 The hard block output has level 2 hysteresis internally 11 The hard block output has level 3 hysteresis internally 38 8 2 CMP Control Register 1 CMPx_C1 Access Superv...

Page 891: ...in mode If the same channel is selected as the reference voltage this bit has no effect 22 CHN6 Channel 6 input enable Channel 6 of the input enable for the round robin checker If CHN6 is set then the...

Page 892: ...power 0 DAC is disabled 1 DAC is enabled 14 VRSEL Supply Voltage Reference Source Select 0 Vin1 is selected as resistor ladder network supply reference Vin 1 Vin2 is selected as resistor ladder networ...

Page 893: ...trol Register 2 CMPx_C2 Access Supervisor read write User read write Address Base address 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RRE RRIE FXMP 0 FXMXCH 0 CH7F CH6F CH5F CH4F C...

Page 894: ...cted as the fixed reference input for the fixed mux port 101 Channel 5 is selected as the fixed reference input for the fixed mux port 110 Channel 6 is selected as the fixed reference input for the fi...

Page 895: ...0kHz then INITMOD should be set to 80us 10us 8 000000 The modulus is set to 64 same with 111111 other values Initialization delay is set to INITMOD round robin clock period ACOn The result of the inpu...

Page 896: ...rates the filtered and synchronized output COUT Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system Synchronization and edge detection are alw...

Page 897: ...only one sample The value of C0 FILTER_CNT must be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized The probability of an incorrect transition is def...

Page 898: ...rising or falling edge of the comparator output or both Assuming the CMP DMA enable bit is not set the following table gives the conditions in which the interrupt request is asserted and deasserted Ta...

Page 899: ...multiplexer which selects an output voltage from one of 256 distinct levels that outputs from DACO It is controlled through the Control register 1 CMP_C1 Its supply reference source can be selected f...

Page 900: ...in a round robin manner In order to meet the comparator stabilization time after the configurable number of operation clocks defined by C2 NSAM the comparison result is sampled for the selected channe...

Page 901: ...o not select the internal reserved channels for round robin by INPSEL and INNSEL NOTE In round robin mode it is suggested to always configure the DAC output as the fixed port reference NOTE In round r...

Page 902: ...rom PSEL 2 0 Channel decoded from MSEL 2 0 Channel 0 7 can be compared with channel 0 72 Trigger Mode 1 x x 0 1 0 x 0 7 DAC Channel sweep CHNx Channel 0 7 can be swept with DAC x x 1 0 1 x 0 7 Channel...

Page 903: ...d In this situation the internal DAC could generate the reference voltage level for Zero point to make the comparison with the other input channel of CMP module and then output the result of logic 0 a...

Page 904: ...window mode and disable the sample mode CMPx_C0 CMPx_C0 CMP_C0_SE_MASK CMP_C0_WE_MASK Then enable the window s generator to produce the WINDOW signal of related module For detailed information about...

Page 905: ...le channels comparison result Channels result Channel 1 Channel 1 2 Channel 1 Channel 2 Channel 3 Channel 1 2 3 Initialization delay Possible interrupt MCU Wake Up Detect comparison result changing Th...

Page 906: ...CMP_C2_FXMXCH 0 CMP_C2_NSAM 0 CMP_C2_INITMOD 0 CMP_C2_RRE_MASK CMP_C2_RRIE_MASK Set all the pre state of round robin checker channel0 7 to 1 CMPx C2 CMPx C2 CMP_C2_ACOn_MASK CMP_C2_CHnF_MASK 0xFF CMP...

Page 907: ...DAC Reference For this device VREFH and VDDA are selectable as the DAC reference VREFH is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input Use DAC0_STATCTRL DACRFS to select...

Page 908: ...AC0 module BUS_CLK Peripheral Interface Clock Registers 39 1 3 Inter connectivity Information The DAC inter connectivity is shown in following diagram Chip specific information for this module Kinetis...

Page 909: ...d on an external pin or set as one of the inputs to the analog comparator op amps or ADC 39 3 Features The features of the DAC module include 2 7 V to 5 5 V operation On chip programmable reference ge...

Page 910: ...l Stop mode 16 word data buffer supported with configurable watermark and multiple operation modes DMA support 39 4 Block diagram The block diagram of the DAC module is as follows Block diagram Kineti...

Page 911: ...CBBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 39 1 DAC block diagram 39 5 Memory map register definition The DAC has registers to control analog comparator and progra...

Page 912: ...0h base 0h offset 4d i where i 0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DATA1 0 DATA0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 913: ...full any write to the FIFO buffer is ignored and read write pointers remain unchanged Address 4003_F000h base 20h offset 4003_F020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DACBFRP DACBF...

Page 914: ...hen DACBFWMF is set When the DAC buffer read pointer reaches the word defined by this field which is 1 4 words away from the upper limit DACBUP DACBFWMF is set This allows user configuration of the wa...

Page 915: ...nterrupt Enable 0 The DAC buffer watermark interrupt is disabled 1 The DAC buffer watermark interrupt is enabled 9 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 0 The DAC buffer read poin...

Page 916: ...ect one of the two reference inputs DACREF_1 and DACREF_2 as the DAC reference voltage Vin by STATCTRL DACRFS See the chip specific DAC information to determine the source options for DACREF_1 and DAC...

Page 917: ...scend by 1 in the next trigger events until 0 is reached Buffer One time Scan mode The read pointer increases by 1 every time the trigger occurs When it reaches the upper limit it stops there If read...

Page 918: ...ill be organized as FIFO 39 6 2 DMA operation When DMA is enabled DMA requests are generated instead of interrupt requests The DMA Done signal clears the DMA request The status register flags are stil...

Page 919: ...age Guide 39 7 1 12 bit DAC Output The output of the DAC can be placed on an external pin or set as input to the analog comparator or ADC CMP0 CMP1 CMP2 ADC0 DAC_OUT 12 bit DAC DAC_no_buff_out DAC_buf...

Page 920: ...resh rate If the waveform frequency is high it could mean considerable amount of CPU load and thus the CPU may need to run at much higher frequency This device includes an on chip DMA controller that...

Page 921: ...er of DAC triggers 1 Number of Pulse Out 1 40 1 1 2 PDB Input Trigger Connections On this device the PDB trigger source selection is implemented through the TRGMUX module For each PDB unit there is on...

Page 922: ...nnel pre trigger and trigger output In this MCU the following PDB back to back operation acknowledgment connections are implemented based on SIM_CHIPCTL PDB_BB_SEL bit setting When SIM_CHIPCTL PDB_BB_...

Page 923: ...er 3 Figure 40 1 PDB0 back to back chain PDB1 CH 0 pre trigger 0 PDB1 CH 0 pre trigger 1 PDB1 CH 0 pre trigger 2 PDB1 CH 0 pre trigger 7 PDB1 CH 0 pre trigger 6 PDB1 CH 0 pre trigger 4 PDB1 CH 0 pre t...

Page 924: ...gger 2 PDB0 CH 0 pre trigger 7 PDB0 CH 0 pre trigger 6 PDB0 CH 0 pre trigger 4 PDB0 CH 0 pre trigger 5 PDB0 CH 0 pre trigger 3 PDB2 CH 0 pre trigger 0 PDB2 CH 0 pre trigger 1 PDB2 CH 0 pre trigger 2 P...

Page 925: ...al trigger inputs are implemented PDB0 DAC external trigger ADC0SC1A_COCO PDB1 DAC external trigger ADC1SC1A_COCO PDB2 DAC external trigger ADC2SC1A_COCO 40 1 3 4 Pulse Out Connection Individual PDB P...

Page 926: ...d with one ADC One trigger output for ADC hardware trigger and up to 8 pre trigger outputs for ADC trigger select per PDB channel Trigger outputs can be enabled or disabled independently One 16 bit de...

Page 927: ...ailable pre trigger per PDB channel m Pre trigger number valid from 0 to M 1 X Total number of DAC interval triggers x DAC interval trigger output number valid from 0 to X 1 Y Total number of Pulse Ou...

Page 928: ...DAC external trigger inputs is chip specific See the chip configuration information for details 40 2 5 Block diagram This diagram illustrates the major components of the PDB Introduction Kinetis KE1x...

Page 929: ...DLY2 POyDLY1 Pulse Generation Pulse Out y PDBPOEN y Pulse Out y DAC interval trigger x From trigger mux TOEx DAC external trigger input Control logic PDB counter DAC interval counter x Figure 40 5 PDB...

Page 930: ...ed in the modulus register and the counting is restarted This enables a continuous stream of pre triggers trigger outputs as a result of a single trigger input event Enabled Bypassed The pre trigger a...

Page 931: ...R W 0000_0000h 40 4 14 944 4003_1150 DAC Interval Trigger n Control register PDB1_DACINTC0 32 R W 0000_0000h 40 4 15 944 4003_1154 DAC Interval n register PDB1_DACINT0 32 R W 0000_0000h 40 4 16 945 4...

Page 932: ...B0_CH0C1 32 R W 0000_0000h 40 4 5 937 4003_6014 Channel n Status register PDB0_CH0S 32 R W 0000_0000h 40 4 6 938 4003_6018 Channel n Delay 0 register PDB0_CH0DLY0 32 R W 0000_0000h 40 4 7 939 4003_601...

Page 933: ...buffers immediately after 1 is written to LDOK 01 The internal registers are loaded with the values from their buffers when the PDB counter CNT MOD 1 CNT delay elapsed after 1 is written to LDOK 10 T...

Page 934: ...100 Counting uses the peripheral clock divided by 16 x MULT the multiplication factor 101 Counting uses the peripheral clock divided by 32 x MULT the multiplication factor 110 Counting uses the perip...

Page 935: ...de 0 PDB operation in One Shot mode 1 PDB operation in Continuous mode 0 LDOK Load OK Writing 1 to LDOK bit updates the MOD IDLY CHnDLYm DACINTx and POyDLY registers with the values previously written...

Page 936: ...D PDB Modulus Specifies the period of the counter When the counter reaches this value it will be reset back to zero If the PDB is in Continuous mode the count begins anew Reading this field returns th...

Page 937: ...is reserved This read only field is reserved and always has the value 0 IDLY PDB Interrupt Delay Specifies the delay value to schedule the PDB interrupt It can be used to schedule an independent inter...

Page 938: ...er a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1 1 PDB channel s corresponding pre trigger asserts when the counter reaches th...

Page 939: ...alues written to the register are written to its internal buffer instead in other words the internal device bus does not write directly to this register The value in this register s internal buffer is...

Page 940: ...el Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits returns the value of internal regist...

Page 941: ...value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address Base address 24h offset 40d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 2...

Page 942: ...el Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits returns the value of internal regist...

Page 943: ...value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address Base address 30h offset 40d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 2...

Page 944: ...ays has the value 0 DLY PDB Channel Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits ret...

Page 945: ...d in other words the internal device bus does not write directly to this register The value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit A...

Page 946: ...n this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address Base address 194h offset 4d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22 21 20...

Page 947: ...1 ADC block PDB channel n pre trigger outputs 0 to M each pre trigger output is connected to ADC hardware trigger select and hardware trigger inputs The pre triggers are used to precondition the ADC b...

Page 948: ...l n is asserted the associated lock of the pre trigger becomes active The associated lock is released by the rising edge of the corresponding ADCnSC1 COCO the ADCnSC1 COCO should be cleared after the...

Page 949: ...TRIG For the trigger input sources implemented in this MCU see chip configuration information 40 5 3 DAC interval trigger outputs PDB can generate the interval triggers for DACs to update their output...

Page 950: ...4 Pulse Out s PDB can generate pulse outputs of configurable width When the PDB counter reaches the value set in POyDLY DLY1 then the Pulse Out goes high When the PDB counter reaches POyDLY DLY2 then...

Page 951: ...d 40 5 5 Updating the delay registers The following registers control the timing of the PDB operation and in some of the applications they may need to become effective at the same time PDB Modulus reg...

Page 952: ...A trigger input event is detected after 1 is written to SC LDOK 11 Either the PDB counter reaches PDB_MOD MOD 1 value or a trigger input event is detected after 1 is written to SC LDOK After 1 is wri...

Page 953: ...rrupts Table 40 4 PDB interrupt summary Interrupt Flags Enable bit PDB Interrupt SC PDBIF SC PDBIE 1 and SC DMAEN 0 PDB Sequence Error Interrupt CHnS ERRm SC PDBEIE 1 40 5 7 DMA If SC DMAEN is set PDB...

Page 954: ...values if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod 4 and so forth If the applications need a really long delay value and use a pre...

Page 955: ...nstantiations FTM instance Number of channels Features usage FTM0 8 FTM enhanced features GTB_EN FTM1 8 FTM enhanced features GTB_EN Quadrature Decoder FTM2 8 FTM enhanced features GTB_EN Quadrature D...

Page 956: ...implementation limitations the frequency of the fixed frequency clock must not exceed 1 2 of the FTM system clock frequency SYS_CLK NOTE The external clock are synchronized by FTM system clock SYS_CLK...

Page 957: ...tion Inputs for details 41 1 3 1 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SIM_FTMOPT0 register The external pin option is selecte...

Page 958: ...LT0 FAULT1 FAULT2 FAULT3 from SIM_FTMOPT0 selection bitfield 41 1 3 2 FTM Hardware Triggers and Synchronization The FlexTimer support external hardware trigger input which can be used for timer dynami...

Page 959: ...trig through the flexible TRGMUX module init_trig hw_trig ext_trig FTM0 init_trig hw_trig ext_trig FTM1 init_trig hw_trig ext_trig FTM2 init_trig hw_trig ext_trig FTM3 PDB0 PDB1 PDB2 TRGMUX init_trig...

Page 960: ...x channels references to channel numbers 6 and 7 do not apply for that instance The FlexTimer module FTM is a two to eight channel timer that supports input capture output compare and the generation o...

Page 961: ...used FlexTimer configuration More than one FlexTimers may be synchronized to provide a larger timer with their counters incrementing in unison assuming the initialization the input clocks the initial...

Page 962: ...perate as pairs with equal outputs pairs with complementary outputs or independent channels with independent outputs The deadtime insertion is available for each complementary pair Generation of match...

Page 963: ...y If the FTM does not need to produce a real time reference or provide the interrupt sources needed to wake the chip from Wait mode the power can then be saved by disabling FTM functions before enteri...

Page 964: ...trol deadtime insertion output mask fault control and polarity control output modes logic input capture mode prescaler 1 2 4 8 16 32 64 or 128 DECAPEN COMBINE0 CPWMS MS0B MS0A ELS0B ELS0A MS1B MS1A EL...

Page 965: ...each FAULTj input may affect all channels selectively since FAULTM 1 0 and FAULTEN control bits are defined for each pair of channels Because there are several FAULTj inputs maximum of 4 for the FTM m...

Page 966: ...hannel n Value FTM3_C0V 32 R W 0000_0000h 41 4 7 981 4002_6014 Channel n Status And Control FTM3_C1SC 32 R W 0000_0000h 41 4 6 979 4002_6018 Channel n Value FTM3_C1V 32 R W 0000_0000h 41 4 7 981 4002_...

Page 967: ..._0000h 41 4 18 1002 4002_6078 Input Capture Filter Control FTM3_FILTER 32 R W 0000_0000h 41 4 19 1004 4002_607C Fault Control FTM3_FLTCTRL 32 R W 0000_0000h 41 4 20 1005 4002_6080 Quadrature Decoder C...

Page 968: ...7 981 4003_801C Channel n Status And Control FTM0_C2SC 32 R W 0000_0000h 41 4 6 979 4003_8020 Channel n Value FTM0_C2V 32 R W 0000_0000h 41 4 7 981 4003_8024 Channel n Status And Control FTM0_C3SC 32...

Page 969: ...FLTPOL 32 R W 0000_0000h 41 4 23 1011 4003_808C Synchronization Configuration FTM0_SYNCONF 32 R W 0000_0000h 41 4 24 1012 4003_8090 FTM Inverting Control FTM0_INVCTRL 32 R W 0000_0000h 41 4 25 1014 40...

Page 970: ...ol FTM1_C4SC 32 R W 0000_0000h 41 4 6 979 4003_9030 Channel n Value FTM1_C4V 32 R W 0000_0000h 41 4 7 981 4003_9034 Channel n Status And Control FTM1_C5SC 32 R W 0000_0000h 41 4 6 979 4003_9038 Channe...

Page 971: ...18 4003_909C Half Cycle Register FTM1_HCR 32 R W 0000_0000h 41 4 28 1020 4003_9200 Mirror of Modulo Value FTM1_MOD_MIRROR 32 R W 0000_0000h 41 4 29 1020 4003_9204 Mirror of Channel n Match Value FTM1_...

Page 972: ...hannel n Value FTM2_C6V 32 R W 0000_0000h 41 4 7 981 4003_A044 Channel n Status And Control FTM2_C7SC 32 R W 0000_0000h 41 4 6 979 4003_A048 Channel n Value FTM2_C7V 32 R W 0000_0000h 41 4 7 981 4003_...

Page 973: ...4003_A208 Mirror of Channel n Match Value FTM2_C1V_MIRROR 32 R W 0000_0000h 41 4 30 1021 4003_A20C Mirror of Channel n Match Value FTM2_C2V_MIRROR 32 R W 0000_0000h 41 4 30 1021 4003_A210 Mirror of C...

Page 974: ...Prescaler Selects one of 16 division factors for the clock used at input filters The new prescaler factor has effect on the next FTM input clock cycle after the new value is updated into the register...

Page 975: ...el 4 PWM enable bit This bit enables the PWM channel output This bit should be set to 0 output disabled when an input mode is used 0 Channel output port is disabled 1 Channel output port is enabled 19...

Page 976: ...OF interrupts Use software polling 1 Enable TOF interrupts An interrupt is generated when TOF equals one 7 RF Reload Flag Set by hardware when FTM counter matches the value of a reload point configure...

Page 977: ...001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 41 4 4 Counter FTMx_CNT The CNT register contains the FTM counter value Reset clea...

Page 978: ...er resets manually this write coherency mechanism Initialize the FTM counter by writing to CNT before writing to the MOD register to avoid confusion about when the first counter overflow will occur Ad...

Page 979: ...x_CnSC field descriptions Field Description 31 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 Reserved This field is reserved This read only field is...

Page 980: ...then writing a 0 to the CHF bit Writing a 1 to CHF has no effect If another event occurs between the read and write operations the write operation has no effect therefore CHF remains set indicating a...

Page 981: ...ignored In output modes writes to the CnV register are done on its write buffer The CnV register is updated with its write buffer value according to Registers updated from write buffers If FTMEN 0 a...

Page 982: ...field is reserved and always has the value 0 INIT Initial Value Of The FTM Counter 41 4 9 Capture And Compare Status FTMx_STATUS The STATUS register contains a copy of the status flag CHF bit in CnSC...

Page 983: ...is reserved and always has the value 0 7 CH7F Channel 7 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 6 CH6F Channel 6 Flag See the register descrip...

Page 984: ...annel 0 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 41 4 10 Features Mode Selection FTMx_MODE This register contains the global enable bit for FTM...

Page 985: ...APTEST Capture Test Mode Enable Enables the capture test mode This field is write protected It can be written only when MODE WPDIS 1 0 Capture test mode is disabled 1 Capture test mode is enabled 3 PW...

Page 986: ...of MOD CV and OUTMASK registers with the value of their write buffer and the FTM counter initialization NOTE The software trigger SWSYNC bit and hardware triggers TRIG0 TRIG1 and TRIG2 bits have a po...

Page 987: ...bles hardware trigger 2 to the PWM synchronization Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal 0 Trigger is disabled 1 Trigger is enabled 5 TRIG1 PWM Synchr...

Page 988: ...es its maximum value MOD register 0 The maximum loading point is disabled 1 The maximum loading point is enabled 0 CNTMIN Minimum Loading Point Enable Selects the minimum loading point to PWM synchron...

Page 989: ...ion occurs 0 The initialization value is 0 1 The initialization value is 1 3 CH3OI Channel 3 Output Initialization Value Selects the value that is forced into the channel output when the initializatio...

Page 990: ...7 6 5 4 3 2 1 0 R 0 CH7OM CH6OM CH5OM CH4OM CH3OM CH2OM CH1OM CH0OM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_OUTMASK field descriptions Field Description 31 8 Reserved This field is reserved This...

Page 991: ...t is forced to its inactive state 2 CH2OM Channel 2 Output Mask Defines if the channel output is masked or unmasked 0 Channel output is not masked It continues to operate normally 1 Channel output is...

Page 992: ...6 Enables the fault control in channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in...

Page 993: ...is write protected It can be written only when MODE WPDIS 1 23 Reserved This field is reserved This read only field is reserved and always has the value 0 22 FAULTEN2 Fault Control Enable For n 4 Ena...

Page 994: ...ULTEN1 Fault Control Enable For n 2 Enables the fault control in channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels...

Page 995: ...ected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in this pair of channels is enabled 5 SYNCEN0 Synchronization Enable For n 0...

Page 996: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DTVALEX 0 DTPS DTVAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_DEADTIME field descri...

Page 997: ...TRIG This register Indicates when a channel trigger was generated Enables the generation of a trigger when the FTM counter is equal to its initial value Selects which channels are used in the generati...

Page 998: ...bled 1 The generation of the channel trigger is enabled 7 TRIGF Channel Trigger Flag Set by hardware when a channel trigger is generated Clear TRIGF by reading EXTTRIG while TRIGF is set and then writ...

Page 999: ...s equal to the CnV register 0 The generation of the channel trigger is disabled 1 The generation of the channel trigger is enabled 1 CH3TRIG Channel 3 Trigger Enable Enables the generation of the chan...

Page 1000: ...itten only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity is active low 5 POL5 Channel 5 Polarity Defines the polarity of the channel output This field is write protect...

Page 1001: ...f the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity is active low 0 POL0 Channel 0 Polarity Defines...

Page 1002: ...t Detection Flag Represents the logic OR of the individual FAULTFj bits where j 3 2 1 0 Clear FAULTF by reading the FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no ex...

Page 1003: ...ains set after the clearing sequence is completed for the earlier fault condition 0 No fault condition was detected at the fault input 1 A fault condition was detected at the fault input 2 FAULTF2 Fau...

Page 1004: ...after the clearing sequence is completed for the earlier fault condition 0 No fault condition was detected at the fault input 1 A fault condition was detected at the fault input 41 4 19 Input Capture...

Page 1005: ...utput state when a fault event happens Address Base address 7Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1006: ...ilter Enable Enables the filter for the fault input This field is write protected It can be written only when MODE WPDIS 1 0 Fault input filter is disabled 1 Fault input filter is enabled 5 FFLTR1EN F...

Page 1007: ...otected It can be written only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fault input This field is write protected It can be writ...

Page 1008: ...0 0 0 FTMx_QDCTRL field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 PHAFLTREN Phase A Input Filter Enable Enables...

Page 1009: ...sed in the Quadrature Decoder mode 0 Phase A and phase B encoding mode 1 Count and direction encoding mode 2 QUADIR FTM Counter Direction In Quadrature Decoder Mode Indicates the counting direction 0...

Page 1010: ...ays has the value 0 11 ITRIGR Initialization trigger on Reload Point This bit controls whether an initialization trigger is generated when a reload point configured by PWMLOAD register is reached cons...

Page 1011: ...a maximum of 32 41 4 23 FTM Fault Input Polarity FTMx_FLTPOL This register defines the fault inputs polarity Address Base address 88h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W...

Page 1012: ...nput indicates a fault 0 FLT0POL Fault Input 0 Polarity Defines the polarity of the fault input This field is write protected It can be written only when MODE WPDIS 1 0 The fault input polarity is act...

Page 1013: ...ion 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 SWSOC Software output control synchronization is activated by the software trigger 0 The softwa...

Page 1014: ...uffer value at all rising edges of FTM input clock 1 CNTIN register is updated with its buffer value by the PWM synchronization 1 Reserved This field is reserved This read only field is reserved and a...

Page 1015: ...0 Inverting is disabled 1 Inverting is enabled 0 INV0EN Pair Channels 0 Inverting Enable 0 Inverting is disabled 1 Inverting is enabled 41 4 26 FTM Software Output Control FTMx_SWOCTRL This register...

Page 1016: ...ware Output Control Value 0 The software output control forces 0 to the channel output 1 The software output control forces 1 to the channel output 12 CH4OCV Channel 4 Software Output Control Value 0...

Page 1017: ...rol Enable 0 The channel output is not affected by software output control 1 The channel output is affected by software output control 3 CH3OC Channel 3 Software Output Control Enable 0 The channel ou...

Page 1018: ...EL CH7SEL CH6SEL CH5SEL CH4SEL CH3SEL CH2SEL CH1SEL CH0SEL W GLDOK Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_PWMLOAD field descriptions Field Description 31 12 Reserved This field is reserved This re...

Page 1019: ...is enabled and it is considered as a reload opportunity 7 CH7SEL Channel 7 Select 0 Channel match is not included as a reload opportunity 1 Channel match is included as a reload opportunity 6 CH6SEL...

Page 1020: ...ss 9Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 HCVAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_HCR field...

Page 1021: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R VAL FRACVAL 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_CnV_MIRROR field descriptions Field Description 31 16 VAL Mirror...

Page 1022: ...the FTM counter After any chip reset CLKS 1 0 0 0 so no clock source is selected The CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bits does...

Page 1023: ...example of the prescaler counter and FTM counter FTM counter 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 2 3 3 1 1 1 1 1 1 1 1 1 selected input clock prescaler counter FTM counting is up PS 2 0 001 CNTIN 0x0000...

Page 1024: ...counter clock MOD 0x0004 TOF bit set TOF bit set TOF bit set TOF bit 4 4 3 2 1 4 3 2 1 0 1 2 3 4 0 1 2 3 4 4 3 CNTIN 0xFFFC in two s complement is equal to 4 period of counting MOD CNTIN 0x0001 x per...

Page 1025: ...egisters meet this requirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM counter is alw...

Page 1026: ...OD defines the final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until i...

Page 1027: ...0 or if CnV 15 1 In this case 0 CPWM is generated The figure below shows the possible counter events when in up down counting mode See Counter events for more details FTM counter 0 0 1 1 1 1 2 2 2 2...

Page 1028: ...TOF bit MOD 0x0000 counter event Figure 41 9 Example when the FTM counter is free running The FTM counter is also a free running counter when FTMEN 1 QUADEN 0 CPWMS 0 CNTIN 0x0000 and MOD 0xFFFF 41 5...

Page 1029: ...will be used to generate the counter event Figure at Up down counting shows the possible counter events FTM counter is reseted see Counter reset or a value different from zero is written at CLKS fiel...

Page 1030: ...ow true pulses set Output on match up 1 0 XX 10 Combine PWM High true pulses set on channel n match and clear on channel n 1 match X1 Low true pulses clear on channel n match and set on channel n 1 ma...

Page 1031: ...ided by 4 which is required to meet Nyquist criteria for signal sampling Writes to the CnV register is ignored in Input Capture mode While in Debug mode the input capture function works as configured...

Page 1032: ...ther divided by 4 in order to reject high frequency glitches When there is a state change in the input signal the counter is reset and starts counting up As long as the new state is stable on the inpu...

Page 1033: ...ilter counter logic output Figure 41 12 Channel input filter example The figure below shows the delay through the input filter logic considering each internal filter element In this example the filter...

Page 1034: ...hen the selected input capture event is detected in a channel in input capture mode with ICRST 1 FTM input clock CNT channel n input CHF bit C n V XX 0x27 selected channel n input event rising edge NO...

Page 1035: ...atch FTM counter CnV TOF bit 0 1 1 1 2 2 3 3 4 4 5 5 0 0 previous value previous value channel n output counter overflow counter overflow counter overflow channel n match channel n match CNT MOD 0x000...

Page 1036: ...DECAPEN 0 COMBINE 0 CPWMS 0 and MSB 1 The EPWM period is determined by MOD CNTIN 0x0001 and the pulse width duty cycle is determined by CnV CNTIN The CHF bit is set and the channel n interrupt is gen...

Page 1037: ...nter overflow when the CNTIN register value is loaded into the FTM counter and it is forced high at the channel n match FTM counter CnV See the following figure TOF bit CHF bit CNT channel n output MO...

Page 1038: ...at the channel n match FTM counter CnV when the FTM counting is down at the begin of the pulse width and when the FTM counting is up at the end of the pulse width This type of PWM signal is called cen...

Page 1039: ...7 8 8 7 7 7 6 6 6 5 5 5 4 4 3 3 2 2 1 0 1 previous value CNT channel n output counter overflow channel n match in down counting channel n match in up counting channel n match in down counting counter...

Page 1040: ...NTIN and at the channel n 1 match FTM counter C n 1 V It is forced high at the channel n match FTM counter C n V See the following figure If ELSB ELSA X 1 then the channel n output is forced high at t...

Page 1041: ...SA X 1 Figure 41 25 Channel n output if CNTIN C n V MOD and CNTIN C n 1 V MOD and C n V C n 1 V FTM counter channel n output with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 MOD C n 1 V C n V CN...

Page 1042: ...B ELSA X 1 MOD C n 1 V C n V CNTIN Figure 41 28 Channel n output if CNTIN C n V MOD and C n V is Almost Equal to CNTIN and C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSB E...

Page 1043: ...d C n 1 V are not between CNTIN and MOD FTM counter 0 duty cycle channel n output with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 100 duty cycle MOD CNTIN C n 1 V C n V Figure 41 31 Channel n o...

Page 1044: ...ELSB ELSA X 1 100 duty cycle 0 duty cycle MOD C n 1 V C n V Figure 41 33 Channel n output if C n V C n 1 V MOD channel n match is ignored FTM counter channel n output with ELSB ELSA 1 0 channel n outp...

Page 1045: ...35 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD C n 1 V channel n output with ELSB ELSA X 1 FTM counter CNTIN channel n output with ELSB ELSA 1 0 C n V MOD Figure 41 36 Channel n output if C...

Page 1046: ...gure 41 37 Channel n output if C n V MOD and CNTIN C n 1 V MOD C n V CNTIN channel n output with ELSB ELSA X 1 channel n output with ELSB ELSA 1 0 FTM counter C n 1 V MOD Figure 41 38 Channel n output...

Page 1047: ...put with ELSB ELSA X 1 0 duty cycle MOD C n V CNTIN C n 1 V Figure 41 40 Channel n output if C n V CNTIN and C n 1 V MOD 41 5 9 1 Asymmetrical PWM In Combine mode the PWM first edge channel n match FT...

Page 1048: ...el n 1 output with COMP 1 channel n 1 output with COMP 0 channel n output with ELSB ELSA X 1 channel n match Figure 41 42 Channel n 1 output in Complementary mode with ELSB ELSA X 1 NOTE The Complemen...

Page 1049: ...mode is not CPWM then MOD or HCR is updated after MOD or HCR register was written and the FTM counter changes from MOD to CNTIN If the FTM counter is at free running counter mode then this update occ...

Page 1050: ...he end of the prescaler counting If SYNCEN 1 then CnV register is updated by the C n V and C n 1 V register synchronization If the selected mode is not output compare and SYNCEN 1 then CnV register is...

Page 1051: ...ritten to it NOTE The HWTRIGMODE bit must be 1 only with enhanced PWM synchronization SYNCMODE 1 41 5 12 2 Software trigger A software trigger event occurs when 1 is written to the SYNC SWSYNC bit The...

Page 1052: ...ent write 1 to SWSYNC bit Figure 41 44 Software trigger event 41 5 12 3 Synchronization Points The synchronization points are points where the registers can be updated with their write buffer by PWM s...

Page 1053: ...MOD register with its buffer value This synchronization is enabled if FTMEN 1 The MOD register synchronization can be done by either the enhanced PWM synchronization SYNCMODE 1 or the legacy PWM synch...

Page 1054: ...bit wait hardware trigger n HWTRIGMODE bit clear TRIGn bit wait the next selected loading point update MOD with its buffer value update MOD with its buffer value HWRSTCNT bit Figure 41 46 MOD registe...

Page 1055: ...1 to TRIG0 bit TRIG0 bit trigger 0 event FTM input clock Figure 41 48 MOD synchronization with SYNCMODE 0 HWTRIGMODE 0 PWMSYNC 0 REINIT 0 and a hardware trigger was used If SYNCMODE 0 PWMSYNC 0 and R...

Page 1056: ...0 PWMSYNC 0 REINIT 1 and a hardware trigger was used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place The S...

Page 1057: ...n mechanism is the same as the MOD register synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCMODE 1 41 5 12 7 OU...

Page 1058: ...e trigger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of FTM input clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by har...

Page 1059: ...trigger event FTM input clock Figure 41 53 OUTMASK synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and software trigger was used write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is...

Page 1060: ...INVCTRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of FTM input clock INVC 0 or by the enhanced PWM synchroniza...

Page 1061: ...rising edge of FTM input clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGMODE bi...

Page 1062: ...SWOCTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of FTM input clock yes 0 1 0 0 no 1 SWOC...

Page 1063: ...tput from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event occurs synchronization event channel n...

Page 1064: ...rdware trigger TRIGn bit 0 0 0 0 0 1 Figure 41 59 FTM counter synchronization flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits acc...

Page 1065: ...counter synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a hardware trigger was used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled hard...

Page 1066: ...elected the channel n output behavior is changed to force high at the beginning of the PWM period force low at the channel n match and force high at the channel n 1 match See the following figure NOTE...

Page 1067: ...TRL register synchronization INV m bit channel n output after the inverting channel n 1 output after the inverting INV m bit selects the inverting to the pair channels n and n 1 channel n output befor...

Page 1068: ...NOTE CH n OCV 1 and CH n 1 OCV 0 SWOCTRL register synchronization SWOCTRL register synchronization write to SWOCTRL register write to SWOCTRL register Figure 41 65 Example of software output control...

Page 1069: ...clock for the DEADTIME delay is the FTM input clock divided by DTPS bits and the DTVALEX 3 0 DTVAL 5 0 bits define the deadtime modulo that is the number of the deadtime prescaler clocks The deadtime...

Page 1070: ...A 1 0 POL n 0 and POL n 1 0 FTM counter channel n 1 match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n output after deadtime insertion channel n 1...

Page 1071: ...hannel n output before deadtime insertion channel n output after deadtime insertion channel n 1 output before deadtime insertion channel n 1 output after deadtime insertion Figure 41 68 Example of the...

Page 1072: ...the following figure FTM counter channel n output before output mask channel n output after output mask the beginning of new PWM cycles configured PWM signal starts to be available in the channel n o...

Page 1073: ...ulse that is shorter than the minimum value selected by FFVAL 3 0 bits filter clock is regarded as a glitch and is not passed on to the edge detector The fault input n filter is disabled when the FFVA...

Page 1074: ...lue of POL n 1 The fault interrupt is generated when FAULTF 1 and FAULTIE 1 This interrupt request remains set until Software clears the FAULTF bit by reading FAULTF bit as 1 and writing 0 to it Softw...

Page 1075: ...POLn 0 NOTE Figure 41 73 Fault control with automatic fault clearing 41 5 17 2 Manual fault clearing If the manual fault clearing is selected FAULTM 1 0 0 1 or 1 0 then the channels output disabled by...

Page 1076: ...put polarity is high so the logical one at the fault input j indicates a fault If FLTjPOL 1 the fault j input polarity is low so the logical zero at the fault input j indicates a fault 41 5 18 Polarit...

Page 1077: ...1 is forced to one is forced to one The following table shows the values that channels n and n 1 are forced by initialization when COMP 1 or DTEN 1 Table 41 14 Initialization behavior when COMP 1 or D...

Page 1078: ...mbine modes channel n output channel n MSA channel n ELSB channel n ELSA channel n 1 MSA channel n 1 ELSB channel n 1 ELSA Figure 41 75 Priority of the features used at the generation of channels n an...

Page 1079: ...RIG 1 d CH0TRIG 1 CH1TRIG 1 CH2TRIG 1 CH3TRIG 1 CH4TRIG 1 CH5TRIG 1 the beginning of new PWM cycles MOD FTM counter C5V FTM counter C4V FTM counter C3V FTM counter C2V FTM counter C1V FTM counter C0V...

Page 1080: ...f trigger generation in the output channel for up down counting mode 41 5 23 Initialization trigger Initialization trigger allows FTM to generate an external trigger in some specific points of FTM cou...

Page 1081: ...x02 0x03 0x04 0x05 initialization trigger FTM counter FTM input clock CNTIN 0x0000 MOD 0x000F ITRIGR 0 Figure 41 79 Initialization trigger is generated when the FTM counting achieves the CNTIN registe...

Page 1082: ...CNT CNTIN CLKS 1 0 0 0 and a value different from zero is written to CLKS 1 0 bits FTM input clock CNT channel n input CHF bit C n V XX 0x27 selected channel n input event rising edge NOTE Channel n...

Page 1083: ...e configured to the Up counting When the Capture Test mode is enabled CAPTEST 1 the FTM counter is frozen and any write to CNT register updates directly the FTM counter see the following figure After...

Page 1084: ...Request Channel Interrupt 0 0 The channel DMA transfer request is not generated The channel interrupt is not generated 0 1 The channel DMA transfer request is not generated The channel interrupt is g...

Page 1085: ...0 C n V 15 0 channel n CHIE FTMEN DECAPEN DECAP channel n MSA channel n ELSB ELSA channel n 1 ELSB ELSA 0 1 channel n input FTM input clock synchronizer CLK D Q filter prescaler CLK D Q filter clock c...

Page 1086: ...SB and channel n 1 ELSA bits are channel n 1 bits The Dual Edge Capture mode must be used with channel n ELSB ELSA 0 1 or 1 0 channel n 1 ELSB ELSA 0 1 or 1 0 and the FTM counter in Free running count...

Page 1087: ...registers For a new sequence of the measurements in the Dual Edge Capture Continuous mode clear the channel n CHF and channel n 1 CHF bits to start new measurements 41 5 26 3 Pulse width measurement I...

Page 1088: ...nnel n 1 CHF C n V channel n 1 CHF bit channel n CHF bit clear channel n CHF 1 Figure 41 86 Dual Edge Capture One Shot mode for positive polarity pulse width measurement The following figure shows an...

Page 1089: ...iod measurement If the channels n and n 1 are configured to capture consecutive edges of the same polarity then the period of the channel n input signal is measured If both channels n and n 1 are conf...

Page 1090: ...t DECAPEN set DECAP clear channel n CHF and clear channel n 1 CHF are made by the user 4 9 11 12 13 14 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 17 20 15 20 23 C n V channel n 1 CHF bit channel n CH...

Page 1091: ...channel n CHF 1 8 12 22 24 11 19 21 23 25 27 23 20 19 17 7 9 11 13 15 6 8 10 12 16 14 24 22 20 18 26 25 21 Figure 41 89 Dual Edge Capture Continuous mode to measure of the period between two consecut...

Page 1092: ...ccurred and the read of C n 1 V returns the FTM counter value when the event 2 occurred read C n 1 V FTM counter channel n input after the filter channel input channel n capture buffer C n V C n 1 V c...

Page 1093: ...ILTER0 register The phase B input filter is enabled by PHBFLTREN bit and this filter s value is defined by CH1FVAL 3 0 bits CH n 1 FVAL 3 0 bits in FILTER0 register The FLTPS 3 0 bits controls both fi...

Page 1094: ...se A and B signals define the counting rate The FTM counter is updated when there is an edge either at the phase A or phase B signals If PHAPOL 0 and PHBPOL 0 then the FTM counter increment happens wh...

Page 1095: ...unter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 4...

Page 1096: ...Quadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications phase A phase B FTM counter MOD CNTIN 0x0...

Page 1097: ...llations 41 5 28 Debug mode When the chip is in Debug mode the BDMMODE 1 0 bits select the behavior of the FTM counter the channel n CHF bit the channels output and the writes to the MOD CNTIN and C n...

Page 1098: ...value except for channels in Output Compare mode In the channels outputs initialization the channel n output is forced to the CH n OI bit value when the value 1 is written to INIT bit See Initializati...

Page 1099: ...rate an initialization trigger and a register reload when a load point is reached Note that Load Frequency configuration can modify the RF generation half cycle match HCSEL counter event channel 0 mat...

Page 1100: ...n up counting The table below shows the possible counter events selection reload opportunities to up down counting mode Table 41 19 Reload opportunities to up down counting mode FTM_SYNC bits Reload o...

Page 1101: ...st select these reload points at the safe points in time 41 5 30 Global Load The global load mechanism allows several modules to have their double buffered registers synchronously reloaded after a syn...

Page 1102: ...M counter enable logic FTM counter enable gtb_out Figure 41 101 Global time base GTB block diagram The GTB functionality is implemented by the GTBEEN and GTBEOUT bits in the CONF register the input si...

Page 1103: ...s 3 Write 1 to CONF GTBEEN and write 0 to CONF GTBEOUT at the same time 4 Select the intended FTM counter clock source in SC CLKS The clock source needs to be consistent across all participating modul...

Page 1104: ...n be used by applications where more resolution than one unit of the FTM counter is needed Two kinds of dithering are available PWM period dithering and edge dithering 41 5 33 1 PWM Period Dithering T...

Page 1105: ...s accumulator overflows that is the result of the adding is greater or equal than 0x20 then one unit of FTM counter is added to the end of the current PWM period and the accumulator remains with the r...

Page 1106: ...0x0001 0x0001 x T 0x000E x T Figure 41 102 PWM Period Dithering with Up Counting Assuming the FTM counter is an up counter T is one unit of FTM counter the PWM period without period dithering is MOD C...

Page 1107: ...od Dithering it is recommended to use C n MOD 1 For the generation of PWM signals in the channel n with channel n ELSB ELSA 2 b10 using Combine mode and PWM Period Dithering it is recommended to use F...

Page 1108: ...using CPWM mode and PWM Period Dithering it is recommended to use C n V 15 0 and C n V MOD 1 and MOD 0x0000 41 5 33 2 PWM Edge Dithering The channel n internal accumulator used in the PWM edge ditheri...

Page 1109: ...ns on the channel n match FTM counter C n V that is its position is not modified by the edge dithering However if there was the overflow of the channel n accumulator in the current EPWM period then th...

Page 1110: ...mal are DC1 50 x T DC2 51 x T average duty cycle 50 5 32 x T 50 15625 x T PWM edge dithering PWM edge dithering PWM edge dithering PWM edge dithering PWM edge dithering Figure 41 106 Example of Averag...

Page 1111: ...Mode with PWM Edge Dithering 41 5 33 2 3 Combine Mode In the Combine mode the PWM edge dithering can be done in the channel n match FTM counter C n V edge or in the channel n 1 match FTM counter C n 1...

Page 1112: ...thering in Combine Mode The channel n 1 match edge dithering is enabled when a non zero value is written to the channel n 1 FRACVAL For the channel n 1 match edge dithering the channel n 1 has an inte...

Page 1113: ...T Combine duty cycle DC1 C n V C n 1 V x T 0x0002 x T Figure 41 109 Channel n 1 Match Edge Dithering in Combine Mode NOTE It is recommended to use only one PWM Edge Dithering channel n PWM Edge Dithe...

Page 1114: ...3 This write updates the FTM counter with the CNTIN register value and the channels output with its initial value except for channels in output compare mode Counter reset The next step is to select t...

Page 1115: ...e and the channel n output is toggled when there is a match C n V 0x0014 00 XX 01 4 use of software output control or initialization to update the channel output to the zero Figure 41 111 FTM behavior...

Page 1116: ...ontrol Do not use the SWOC without SW synchronization see item 6 Do not use the Inverting without SW synchronization see item 6 Do not use the Initialization Do not change the polarity control Do not...

Page 1117: ...er has multiple sources of interrupt However these sources are OR d together to generate a single interrupt request per FTM module to the interrupt controller When an FTM interrupt occurs read the FTM...

Page 1118: ...on function The SIM_FTMOPT1 register has control bits FTMxCHySEL that allow the user to select normal PWM Output Compare mode on the corresponding FTM timer channel or modulate with FTM1_CH1 The diagr...

Page 1119: ...of the FTM module could be used as the GTB_EN source The global timer base only allows the FTM counters to start their operation synchronously it does not automatically provide continuous synchroniza...

Page 1120: ...nd debug halt mode In the FTM chapter references to the chip being in BDM are the same as the chip being in debug halt mode Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1120 NXP...

Page 1121: ...The LPIT generates periodic trigger events to the DMA Mux as shown in the table below Table 42 1 LPIT channel assignments for periodic DMA triggering DMA Channel Number LPIT Channel 0 0 1 1 2 2 3 3 4...

Page 1122: ...ce Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C FlexIO and LPIT 42 1 3 Inter connectivity Inform...

Page 1123: ...together The LPIT can operate in low power modes if configured to do so The pre trigger and trigger outputs can be used to trigger other modules on the device Each timer channel can be configured to...

Page 1124: ...ock Diagram LPIT IPS Bus Interface Global Registers Channel Registers Interrupt Bus Clock IPS Bus Global Synchronizers Timer Freeze Trig Out 0 Pre Trig Out 0 Low Power Clock Gate Timer Channel 0 Timer...

Page 1125: ...ectness of programmed values in the registers and software must ensure that correct values are being written LPIT memory map Absolute address hex Register name Width in bits Access Reset value Section...

Page 1126: ...2 4 8 1133 4003_7054 Current Timer Value LPIT0_CVAL3 32 R FFFF_FFFFh 42 4 9 1134 4003_7058 Timer Control Register LPIT0_TCTRL3 32 R W 0000_0000h 42 4 10 1135 42 4 1 Version ID Register LPITx_VERID Add...

Page 1127: ...on 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 8 EXT_TRIG Number of External Trigger Inputs Number of external triggers implemented CHANNEL Num...

Page 1128: ...eset 0 M_CEN Module Clock Enable Enables the peripheral clock to the module timers M_CEN bit must be asserted when writing to timer registers Both clocks bus clock and peripheral clock must be enabled...

Page 1129: ...mpare modes sets to 1 at the end of the timer period In capture modes sets to 1 when the trigger asserts Writing logic 1 to this flag clears it Writing 0 has no effect 0 Timer has not timed out 1 Time...

Page 1130: ...if corresponding Timer Interrupt Flag is asserted 0 Interrupt generation is disabled 1 Interrupt generation is enabled 1 TIE1 Channel 1 Timer Interrupt Enable Enables interrupt generation when this b...

Page 1131: ...d is reserved and always has the value 0 3 SET_T_EN_3 Set Timer 3 Enable Writing 1 to this bit will enable the timer channel 3 This bit can be used in addition to T_EN bit in TCTRL3 register Writing a...

Page 1132: ...used in addition to T_EN bit in TCTRL0 register Writing a 0 will not disable the counter This bit will be cleared when T_EN bit in TCTRL0 is set to 0 or 1 is written to the CLR_T_EN_0 bit in CLRTEN re...

Page 1133: ...er Writing a 1 will not enable the counter This bit is self clearing and will always read 0 0 No Action 1 Clear T_EN bit for Timer Channel 1 0 CLR_T_EN_0 Clear Timer 0 Enable Writing a 1 to this bit w...

Page 1134: ...serts 0 Invalid load value in compare modes 0 Value to be loaded Compare Mode or Value of Timer Capture Mode 42 4 9 Current Timer Value LPITx_CVALn These registers indicate the current timer counter v...

Page 1135: ...er from the set of internal or external triggers selected by TRG_SRC 0 Timer channel 0 trigger source is selected 1 Timer channel 1 trigger source is selected 2 Timer channel 2 trigger source is selec...

Page 1136: ...the timer starts decrementing 0 Timer starts to decrement immediately based on restart condition controlled by TSOI bit 1 Timer starts to decrement when rising edge on selected trigger is detected 15...

Page 1137: ...are Mode set the timer timeout value by programming the appropriate value in TVAL register for those channels Configure TIEn bits in MIER register for those channels which are required to generate int...

Page 1138: ...rol bits TSOT TSOI TROT which control the timer load reload start and restart of the timers NOTE The trigger output is asserted one Protocol Timer Clock cycle later than pre trigger output The trigger...

Page 1139: ...ained together to achieve a larger value of timeout Chaining the timer channel causes them to work in a nested loop manner thereby leading to an effective timeout value of TVALCHn TVALCHn 1 1 The chan...

Page 1140: ...0_TVAL0 ONE_SECOND_VALUE LPIT0_MIER LPIT_MIER_TIE0_MASK NVIC_EnableIRQ LPIT0_IRQ LPIT0_SETTEN LPIT_SETTEN_SET_T_EN_0_MASK 42 6 2 LPIT ADC Trigger The LPIT could be used as an alternate ADC hardware tr...

Page 1141: ...and doze modes and enable LPIT module Setup the LPIT_CH0 and LPIT_CH1 counters mode to 32 bit Periodic Counter and keep default values for the trigger source Set timer period for LPIT_CH0 and LPIT_CH...

Page 1142: ...DE 0 LPIT0_TVAL0 ADC_PRETRG_DELAY_VALUE1 LPIT0_TVAL1 ADC_PRETRG_DELAY_VALUE2 LPIT0_SETTEN LPIT_SETTEN_SET_T_EN_0_MASK LPIT_SETTEN_SET_T_EN_1_MASK SIM_ADCOPT SIM_ADCOPT_ADC0TRGSEL 1 SIM_ADCOPT_ADC0PRET...

Page 1143: ...f PWT has two selectable clocks sources and support up to BUS_CLK with internal timer clock PWT module supports programmable positive or negative pulse edges and programmable interrupt generation upon...

Page 1144: ...LK1 TCLK2 43 1 3 Inter connectivity Information PWT module has four input channels which is connected as shown in the following table Table 43 1 PWT input connections PWT input channel Connection 0 TR...

Page 1145: ...ative pulse width measurements Programmable measuring time between successive alternating edges rising edges or falling edges Programmable pre scaler from clock input as 16 bit counter time base Two s...

Page 1146: ...resets If stop exits with another source the module resumes operation based on module status upon exit Active Background Mode Upon entering BDM mode the PWT suspends all counting and pulse edge detec...

Page 1147: ...SYNC PWTIN2 PWTIN0 PINSEL 1 0 PWTIN PWTIN3 Decode PINEN0 MUX PINEN1 PINEN2 PINEN3 PWTLVL Figure 43 1 Pulse width timer PWT block diagram External signal description 43 3 1 Overview PWT has the follow...

Page 1148: ...ourth of the bus frequency The ALTCLK pin can be shared with a general purpose port pin See the Pins and Connections chapter for the pin location and priority of this function Memory Map and Register...

Page 1149: ...o generate interrupt when PWTRDY is set 1 Enable PWT to generate interrupt when PWTRDY is set 4 POVIE PWT Counter Overflow Interrupt Enable Enables disables the PWT to generate an interrupt when PWTOV...

Page 1150: ...43 4 2 Pulse Width Timer Control Register PWT_CR Address 4005_6000h base 1h offset 4005_6001h Bit 7 6 5 4 3 2 1 0 Read PCLKS PINSEL TGL LVL PRE Write w1c Reset 0 0 0 0 0 0 0 0 PWT_CR field description...

Page 1151: ...divided by 8 100 Clock divided by 16 101 Clock divided by 32 110 Clock divided by 64 111 Clock divided by 128 43 4 3 Pulse Width Timer Positive Pulse Width Register High PWT_PPH Address 4005_6000h bas...

Page 1152: ...ptions Field Description NPWH Negative Pulse Width 15 8 High byte of captured negative pulse width value 43 4 6 Pulse Width Timer Negative Pulse Width Register Low PWT_NPL Address 4005_6000h base 5h o...

Page 1153: ...field descriptions Field Description PWTL PWT counter 7 0 Low byte of PWT counter register Functional description 43 5 1 PWT counter and PWT clock pre scaler The pulse width timer PWT measures durati...

Page 1154: ...t free counter will begin to count up until a edge transistion on the selected PWTIN Determined by PWT_CS FCTLE and PWTIN state the counter contents can be uploaded to the corresponding registers If P...

Page 1155: ...11 12 0x0 0x0 0xD1 0xD2 0x00 0xD1 0x00 0xD2 0x00 0x00 PWTEN FCTLE 0 PWTIN NPH L PPH L READY CNTH L Figure 43 2 PWT normal measurement with FCTLE 0 1 2 3 4 5 6 7 8 9 10 11 12 0x0 0x0 0xD4 0xD3 0x00 0xD...

Page 1156: ...FCTLE 1 1 2 3 4 5 6 7 8 9 10 11 12 PWTEN PWTIN PWTOV TGL LVL CNTH L 0x00 0xFFFF Figure 43 5 PWT measurement overflows with PWTIN toggles 1 2 3 4 5 6 7 8 9 10 11 12 0x00 0xFFFF PWTEN PWTIN PWTOV TGL LV...

Page 1157: ...ter If another pulse measurement is completed and the pulse width registers are updated the clearing of the PWTRDY flag fails i e the PWTRDY will still be set but the 16 bit read buffer s will be upda...

Page 1158: ...re is no missing count the PWTxCNTH L and the clock pre scaler output are reset in a bus clock cycle after the completion of a pulse width measurement Reset overview 43 6 1 Description of reset operat...

Page 1159: ...s except that the reset state will be held until the PWTEN bit is set to 1 Interrupts 43 7 1 Description of interrupt operation The other major component of the PWT is the interrupts control logic Whe...

Page 1160: ...0 0 212223 err 1 pwtclk 1 bus clock Figure 43 8 Example at PWTCLK is bus clock divided by 1 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 1011 counter read result 11 pwtclk counter read result 11 pwtc...

Page 1161: ...th 2 pwtclk err 0 err 1 pwtclk 1 bus clock 0 1 2 Figure 43 11 Example at PWTCLK is bus clock divided by 8 43 8 Initialization Application information Following are the recommended steps to initialize...

Page 1162: ...pture control and period measurement PWT typical usage is external signal input capture and time period measurement Example PWT input channel 1 capture external signal and measure its time period Enab...

Page 1163: ..._CR PWT_CR_PCLKS 0 PWT_CR_PRE 0 PWT_CR_PINSEL 1 PWT_CS PWT_CS_PWTEN_MASK EnableIRQ PWT_IRQ Chapter 43 Pulse Width Timer PWT Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 NXP Semiconductors 1...

Page 1164: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1164 NXP Semiconductors...

Page 1165: ...e input clock sources available for this module Peripheral Clocking LPTMR PCC_LPTMRx CGC PCC module DIV2 DIV2 DIV2 DIV2 SOSC PLL FIRC SIRC SCG module SCG DIVBUS PLLDIV2_CLK SOSCDIV2_CLK SIRCDIV2_CLK F...

Page 1166: ...R TPS Pulse counter input number Chip input 00 0 TRGMUX output 01 1 LPTMR0_ALT1 pin 10 2 LPTMR0_ALT2 pin 11 3 LPTMR0_ALT3 pin TRGMUX LPTMRx_HW_TRG LPTMRx LPTMRx_ALT2 LPTMRx_ALT1 LPTMRx_ALT3 PERIPHERAL...

Page 1167: ...k source for prescaler glitch filter Configurable input source for pulse counter Rising edge or falling edge 44 2 2 Modes of operation The following table describes the operation of the LPTMR module i...

Page 1168: ...Timing Assertion or deassertion may occur at any time input may assert asynchronously to the bus clock 44 4 Memory map and register definition NOTE The LPTMR registers are reset only on a POR or LVD e...

Page 1169: ...LPTMR is enabled and the CNR equals the CMR and increments TCF is cleared when the LPTMR is disabled or a logic 1 is written to it 0 The value of CNR is not equal to CMR and increments 1 The value of...

Page 1170: ...PTMR is disabled 0 Time Counter mode 1 Pulse Counter mode 0 TEN Timer Enable When TEN is clear it resets the LPTMR internal logic including the CNR and TCF When TEN is set the LPTMR is enabled While w...

Page 1171: ...ler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 rising clock edges 1011 Prescaler divides the prescaler clock by 4096 glitch filter recognizes change on...

Page 1172: ...ardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger will remain asserted until the LPTMR is disabled If the LPTMR is enabled the CMR must be altered onl...

Page 1173: ...E The clock source selected may need to be configured to remain enabled in low power modes otherwise the LPTMR will not operate during low power modes In Pulse Counter mode with the prescaler glitch f...

Page 1174: ...PTMR is first enabled the output of the glitch filter is asserted that is logic 1 for active high and logic 0 for active low The following table shows the change in glitch filter output with the selec...

Page 1175: ...escaler bypassed Prescaler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with g...

Page 1176: ...c 1 to it CSR TIE can be altered and CSR TCF can be cleared while the LPTMR is enabled The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any...

Page 1177: ...put pulses on LPTMR0_ALT1 pin Enable the LPTMR module clock Configure LPTMR to Pulse counter mode use LPO 128K as clock source bypass the glitch filter Set the compare value register to the value you...

Page 1178: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1178 NXP Semiconductors...

Page 1179: ...fore the related register bitfields are not applicable e g RTC_CR WPS RTC_CR WPE and RTC_IER WPON NOTE Also there is no integrated capacitor for this device therefore no tunable capacitors included in...

Page 1180: ...Registers OSC32_CLK Counter LPO 1kHz RTC_CLKIN 32kHz SOSC_CLK RTC_CR LPOS SIM_CHIPCTL RTC_CLKSEL 45 1 3 Inter connectivity Information The SRTC inter connectivity is shown in following diagram Chip sp...

Page 1181: ...e 32 bit seconds counter with roll over protection and 32 bit alarm 16 bit prescaler with compensation that can correct errors between 0 12 ppm and 3906 ppm Option to increment prescaler using the LPO...

Page 1182: ...e prescaler output configurable to 1 2 4 8 16 32 64 or 128 Hz or the 32 kHz crystal clock 45 3 Register definition All registers must be accessed using 32 bit writes and all register accesses incur th...

Page 1183: ...00h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TSR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TSR field descriptions F...

Page 1184: ...eld descriptions Field Description TAR Time Alarm Register When the time counter is enabled the SR TAF is set whenever the TAR TAR equals the TSR TSR and the TSR TSR increments Writing to the TAR clea...

Page 1185: ...to configure for a compensation interval of one second This register is double buffered and writes do not take affect until the end of the current compensation interval TCR Time Compensation Register...

Page 1186: ...field is reserved This read only field is reserved and always has the value 0 25 24 CPE Clock Pin Enable NOTE The CPE field should be configured to 01 or 11 i e CPE 0 1 if we want the RTC_CLKOUT signa...

Page 1187: ...rements using LPO bits 4 0 of the prescaler are bypassed 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 CPS Clock Pin Select 0 The prescaler output clo...

Page 1188: ...do not increment When time counter is enabled the TSR register and TPR register are not writeable but increment 0 Time counter is disabled 1 Time counter is enabled 3 Reserved This field is reserved...

Page 1189: ...ed This read only field is reserved and always has the value 0 7 Reserved This field is reserved This read only field is reserved and always has the value 1 6 LRL Lock Register Lock After being cleare...

Page 1190: ...R 0 TSIC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 WPON Reserved TSIE Reserved TAIE TOIE TIIE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 RTC_IER field descript...

Page 1191: ...terrupt vector It is generated once a second and requires no software overhead there is no corresponding status flag to clear 0 Seconds interrupt is disabled 1 Seconds interrupt is enabled 3 Reserved...

Page 1192: ...k Register Write After being cleared this bit is set only by system reset It is not affected by software reset 0 Writes to the Lock Register are ignored 1 Writes to the Lock Register complete as norma...

Page 1193: ...t 0 Writes to the Time Seconds Register are ignored 1 Writes to the Time Seconds Register complete as normal 45 3 10 RTC Read Access Register RTC_RAR Address 4003_D000h base 804h offset 4003_D804h Bit...

Page 1194: ...ation Register are ignored 1 Reads to the Time Compensation Register complete as normal 2 TARR Time Alarm Register Read After being cleared this bit is set only by system reset It is not affected by s...

Page 1195: ...e reset by the chip reset 45 4 1 3 Supervisor access When the supervisor access control bit is clear only supervisor mode software can write to the RTC registers non supervisor mode software will gene...

Page 1196: ...as high as 3906 ppm and as low as 0 12 ppm The compensation factor must be calculated externally to the RTC and supplied by software to the compensation register The RTC itself does not calculate the...

Page 1197: ...ill usually be the next alarm value although writing a value that is less than TSR such as 0 will prevent SR TAF from setting again SR TAF cannot otherwise be disabled although the interrupt it genera...

Page 1198: ...generated once a second and requires no software overhead there is no corresponding status flag to clear It is enabled in the RTC by the time seconds interrupt enable bit and enabled at the chip level...

Page 1199: ...C initialized user can set the date time before starting the timer Please make sure the timer is stopped when setting the date time by RTC_TSR register stop timer first RTC_SR RTC_SR_TCE_MASK convert...

Page 1200: ...er output configurable to 1 2 4 8 16 32 64 or 128 Hz or 32 kHz output derived from RTC oscillator as shown below RTC_CR CPS RTC_CLKOUT RTC 1 2 4 8 16 32 64 128 Hz clock configurable via RTC_IER TSIC R...

Page 1201: ...onfiguration TX FIFO word 32bit RX FIFO word 32bit Chip Selects LPSPI0 4 4 4 LPSPI1 4 4 4 NOTE The TX RX FIFO word does not refer to system bus width 32 bit and it varies for different communication m...

Page 1202: ...2_CLK SOSCDIV2_CLK SIRCDIV2_CLK FIRCDIV2_CLK LPUARTx module BUS_CLK Peripheral Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies simi...

Page 1203: ...Interface SPI module that supports an efficient interface to an SPI bus as a master and or a slave The LPSPI can continue operating in stop modes provided an appropriate clock is available and is des...

Page 1204: ...us Clock External Clock Functional Clock Clock Domains Command TX FIFO RX FIFO Shift Register SCK PCS 3 0 Everywhere else Figure 46 1 Block Diagram 46 2 4 Modes of operation The LPSPI module supports...

Page 1205: ...when used as Host Request output in master mode I O PCS 2 DATA 2 Peripheral Chip Select or data pin 2 during quad data transfers Input in slave mode output in master mode input in quad data receive tr...

Page 1206: ...tatus Register LPSPI0_FSR 32 R 0000_0000h 46 3 13 1219 4002_C060 Transmit Command Register LPSPI0_TCR 32 R W 0000_001Fh 46 3 14 1220 4002_C064 Transmit Data Register LPSPI0_TDR 32 W 0000_0000h 46 3 15...

Page 1207: ...1225 46 3 1 Version ID Register LPSPIx_VERID Address Base address 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAJOR MINOR FEATURE W Reset 0 0...

Page 1208: ...0 0 0 0 0 0 0 1 0 LPSPIx_PARAM field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 8 RXFIFO Receive FIFO Size The...

Page 1209: ...field is reserved and always has the value 0 9 RRF Reset Receive FIFO 0 No effect 1 Receive FIFO is reset 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit FIFO is reset 7 4 Reserved This field is rese...

Page 1210: ...10 9 8 7 6 5 4 3 2 1 0 R 0 DMF REF TEF TCF FCF WCF 0 RDF TDF W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LPSPIx_SR field descriptions Field Description 31 25 Reserved This field is...

Page 1211: ...en the PCS negates 0 Frame transfer has not completed 1 Frame transfer has completed 8 WCF Word Complete Flag This flag will set when the last bit of a received word is sampled 0 Transfer word not com...

Page 1212: ...Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 11 TEIE Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 10 TCIE Transfer Complete Interrupt Enable 0 Interrupt...

Page 1213: ...4 3 2 1 0 R 0 RDDE TDDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_DER field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the...

Page 1214: ...ed unless the DMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be emptied as normal but once the LPSPI is i...

Page 1215: ...CFG 0 MATCFG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PCSPOL 0 NOSTALL AUTOPCS SAMPLE MASTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_CFGR1 field des...

Page 1216: ...eserved This field is reserved This read only field is reserved and always has the value 0 11 8 PCSPOL Peripheral Chip Select Polarity Configures the polarity of each Peripheral Chip Select pin 0 The...

Page 1217: ...lave mode 1 Master mode 46 3 9 Data Match Register 0 LPSPIx_DMR0 Address Base address 30h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MATCH0 W Re...

Page 1218: ...he minimum delay is 1 cycle 15 8 DBT Delay Between Transfers Configures the delay in master mode from the PCS negation to the next PCS assertion The delay is equal to DBT 2 cycles of the LPSPI functio...

Page 1219: ...ta Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER Writing a value equal or greater than the FIFO size will be truncated 46 3 13 FIFO Status Register LPSPIx...

Page 1220: ...e an existing frame has completed then the existing frame will terminate and the command word will then update The command word can be changed during a continuous transfer provided CONTC of the new co...

Page 1221: ...ansfer This field is only updated between frames 00 Transfer using LPSPI_PCS 0 01 Transfer using LPSPI_PCS 1 10 Transfer using LPSPI_PCS 2 11 Transfer using LPSPI_PCS 3 23 LSBF LSB First 0 Data is tra...

Page 1222: ...ster mode this bit will initiate a new transfer which cannot be aborted by another command word and the bit will be cleared by hardware at the end of the transfer 00 Normal transfer 01 Mask transmit d...

Page 1223: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W DATA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_TDR field descriptions Field Description DATA Transmit Data B...

Page 1224: ...s Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RXEMPTY RX FIFO Empty 0 RX FIFO is not empty 1 RX FIFO is empty 0 SOF Start Of Fr...

Page 1225: ...ansfers in both master and slave modes If the functional clock is disabled in slave mode the LPSPI can transfer a single word before the functional clock needs to be enabled The LPSPI divides the func...

Page 1226: ...F A FIFO is empty after being reset 46 4 2 Master Mode 46 4 2 1 Transmit and Command FIFO The transmit and command FIFO is a combined FIFO that includes both transmit data and command words Command wo...

Page 1227: ...ed on FRAMESZ configuration and the TXMSK bit will be cleared at the end of the transfer The following table describes the attributes that are controlled by the command word Table 46 3 LPSPI Command W...

Page 1228: ...ansfers in either half duplex or full duplex data formats Two and four bit transfers are useful for interfacing to QuadSPI memory devices and only support half duplex data formats at least one of TXMS...

Page 1229: ...function that can match received data against one of two words or against a masked data word The data match function can also be configured to compare only the first one or two received data words sin...

Page 1230: ...rds of a SPI bus transfer 0 1 cycle 255 256 cycles PCSSCK Configures the minimum delay between PCS assertion and the first SCK edge to PCSSCK 1 cycles 0 1 cycle 255 256 cycles SCKPCS Configures the mi...

Page 1231: ...nd configured by PCSPOL If PCSCFG is set then PCS 3 2 should not be selected LSBF Configures if LSB bit 0 or MSB bit 31 for a 32 bit word is transmitted received first BYSW Enables byte swap on each 3...

Page 1232: ...h received data against one of two words or against a masked data word The data match function can also be configured to compare only the first one or two received data words since the start of the fr...

Page 1233: ...sampled Y N Y FCF Frame complete PCS has negated Y N Y TCF Transfer complete PCS has negated and transmit command FIFO is empty Y N Y TEF Transmit error flag indicates transmit command FIFO underrun...

Page 1234: ...CS negates and remains asserted until PCS next asserts The word output trigger asserts at the end of each received word and remains asserted for one LPSPI_SCK period 46 4 5 2 Input Trigger The LPSPI i...

Page 1235: ...S mode provided the clock it is using remains enabled Table 47 1 LPI2C Configuration TX FIFO word 8bit RX FIFO word 8bit SMBus Slave mode enable LPI2C0 4 4 Yes Yes LPI2C1 4 4 Yes Yes 47 1 2 Module Clo...

Page 1236: ...al Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C FlexIO and LPIT 47 1 3 Inter connectiv...

Page 1237: ...n I2C bus as a master and or a slave The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register...

Page 1238: ...can be used to control the start time of an I2C bus transfer Flexible receive data match can generate interrupt on data match and or discard unwanted data Flag and optional interrupt to signal Repeat...

Page 1239: ...uration Registers Slave Logic SDAS SCLS Glitch Filter Bus Clock External Clock Functional Clock Clock Domains Command TX FIFO Figure 47 1 LPI2C block diagram 47 2 4 Modes of operation The LPI2C module...

Page 1240: ...red to use separate pins this the LPI2C slave SCL pin I O SDAS Secondary I2C data line In 4 wire mode this is the SDA output pin If LPI2C master slave are configured to use separate pins this the LPI2...

Page 1241: ...00_4000h 47 3 17 1259 4006_6110 Slave Control Register LPI2C0_SCR 32 R W 0000_0000h 47 3 18 1260 4006_6114 Slave Status Register LPI2C0_SSR 32 R W 0000_0000h 47 3 19 1261 4006_6118 Slave Interrupt Ena...

Page 1242: ...FO Control Register LPI2C1_MFCR 32 R W 0000_0000h 47 3 14 1257 4006_705C Master FIFO Status Register LPI2C1_MFSR 32 R 0000_0000h 47 3 15 1257 4006_7060 Master Transmit Data Register LPI2C1_MTDR 32 W 0...

Page 1243: ...ield returns the major version number for the specification 23 16 MINOR Minor Version Number This read only field returns the minor version number for the specification FEATURE Feature Specification N...

Page 1244: ...Transmit FIFO Size The number of words in the master transmit FIFO is 2 MTXFIFO 47 3 3 Master Control Register LPI2Cx_MCR Address Base address 10h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 1245: ...re Reset Reset all internal master logic and registers except the Master Control Register Remains set until cleared by software 0 Master logic is not reset 1 Master logic is reset 0 MEN Master Enable...

Page 1246: ...mpt to send or receive data without first generating a repeated START condition This can occur if the transmit FIFO underflows when the AUTOSTOP bit is set When this flag is set the LPI2C master will...

Page 1247: ...s reserved and always has the value 0 1 RDF Receive Data Flag The Receive Data Flag is set whenever the number of words in the receive FIFO is greater than RXWATER 0 Receive Data is not ready 1 Receiv...

Page 1248: ...Interrupt disabled 1 Interrupt enabled 10 NDIE NACK Detect Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 9 SDIE STOP Detect Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 8 EPIE...

Page 1249: ...0 0 0 0 0 0 0 0 0 0 LPI2Cx_MDER field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RDDE Receive Data DMA Enable 0 D...

Page 1250: ...ess the RMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be emptied as normal but once the LPI2C master is...

Page 1251: ...INCFG 0 MATCFG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TIMECFG IGNACK AUTOSTOP 0 PRESCALE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MCFGR1 field desc...

Page 1252: ...meout Configuration 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured time...

Page 1253: ...nt is not affected by the PRESCALE configuration and is automatically bypassed in High Speed mode 23 20 Reserved This field is reserved This read only field is reserved and always has the value 0 19 1...

Page 1254: ...This field is reserved This read only field is reserved and always has the value 0 47 3 11 Master Data Match Register LPI2Cx_MDMR Address Base address 40h offset Bit 31 30 29 28 27 26 25 24 23 22 21...

Page 1255: ...e setup and hold time for a repeated START condition and setup time for a STOP condition The setup time is extended by the time it takes to detect a rising edge on the external SCL pin Ignoring any ad...

Page 1256: ...21 16 SETHOLD Setup Hold Delay Minimum number of cycles minus one that is used by the master as the setup and hold time for a repeated START condition and setup time for a STOP condition The setup ti...

Page 1257: ...ata Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER Writing a value equal or greater than the FIFO size will be truncated 47 3 15 Master FIFO Status Registe...

Page 1258: ...0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MTDR field descriptions Field Description 31 11 Reserved This field is reserved 10 8 CMD Command Data 000 Transmit DATA 7 0 001 Receive DATA 7 0 1 bytes 010 Generate...

Page 1259: ...only field is reserved and always has the value 0 14 RXEMPTY RX Empty 0 Receive FIFO is not empty 1 Receive FIFO is empty 13 8 Reserved This field is reserved This read only field is reserved and alwa...

Page 1260: ...0 9 RRF Reset Receive FIFO 0 No effect 1 Receive Data Register is now empty 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit Data Register is now empty 7 6 Reserved This field is reserved This read o...

Page 1261: ...28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 BBF SBF 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SARF GCF AM1F AM0F FEF BEF SDF RSF 0 TAF AVF RDF TDF W w1c w1c...

Page 1262: ...eared by reading the Address Status Register This flag cannot generate an asynchronous wakeup 0 Have not received ADDR1 or ADDR0 ADDR1 range matching address 1 Have received ADDR1 or ADDR0 ADDR1 range...

Page 1263: ...writing the transmit ACK register 0 Transmit ACK NACK is not required 1 Transmit ACK NACK is required 2 AVF Address Valid Flag This flag is cleared by reading the address status register When RXCFG is...

Page 1264: ...value 0 15 SARIE SMBus Alert Response Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 14 GCIE General Call Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 13 AM1F Address Match 1...

Page 1265: ...rupt disabled 1 Interrupt enabled 1 RDIE Receive Data Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 0 TDIE Transmit Data Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 47 3 21 S...

Page 1266: ...enabled 47 3 22 Slave Configuration Register 1 LPI2Cx_SCFGR1 The SCFGR1 should only be written when the I2C Slave is disabled Address Base address 124h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20...

Page 1267: ...clear the receive data flag 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag Reading the receive data re...

Page 1268: ...tching occurs following the 9th bit and is therefore compatible with high speed mode 0 Clock stretching disabled 1 Clock stretching enabled 1 RXSTALL RX SCL Stall Enables SCL clock stretching when rec...

Page 1269: ...ilter cycle count is not affected by the PRESCALE configuration and is disabled in high speed mode 15 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13...

Page 1270: ...erved This read only field is reserved and always has the value 0 47 3 25 Slave Address Status Register LPI2Cx_SASR Address Base address 150h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 1271: ...only field is reserved and always has the value 0 0 TXNACK Transmit NACK When NACKSTALL is set must be written once for each matching address byte and each received word Can also be written when LPI2...

Page 1272: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SOF RXEMPTY 0 DATA W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_SRDR field descriptions Field Description 31 16 Reserved This field is reserved This read only f...

Page 1273: ...and data hold time configurations The LPI2C master divides the functional clock by a prescaler and the resulting frequency must be at least eight times faster than the I2C bus bandwidth 47 4 1 2 Exter...

Page 1274: ...l slave logic and registers to their default state except for the SCR itself 47 4 1 6 FIFO reset The LPI2C master implements write only control bits that resets the transmit FIFO MCR RTF and receive F...

Page 1275: ...ode master code must be followed by a STOP or repeated START condition 47 4 2 2 Master Operation Whenever the LPI2C is enabled it monitors the I2C bus to detect when the I2C bus is idle MSR BBF The I2...

Page 1276: ...two bytes or against a masked data byte The data match function can also be configured to compare only the first one or two received data words since the last repeated START condition Receive data tha...

Page 1277: ...the pin input digital filter setting which are configured separately for SCL and SDA divided by the prescaler since the pin input digital filters are not affected by the prescaler setting The followi...

Page 1278: ...0 0x0 0x0 0x02 0x05 0x03 0x01 The formula to calculate number of cycles per bit is as follows Baud rate divide CLKLO CLKHI 2 2 PRESCALER ROUNDDOWN 2 FILTSCL 2 PRESCALER This assumes SCL will pull high...

Page 1279: ...ull up required in the I2C specification The LPI2C master also supports the output only push pull function required for I2C ultra fast mode using the LPI2C_SDA and LPI2C_SCL pins Support for ultra fas...

Page 1280: ...fered and only update during a slave transmit and slave receive transfer respectively The slave address that was received can be configured to be read from either the receive data register for example...

Page 1281: ...SCL hold time when clock stretching is enabled to increase setup time when sampling SDA externally SCL glitch filter time SDA glitch filter time The LPI2C slave imposes the following restrictions on t...

Page 1282: ...r interrupt and LPI2C master transmit receive DMA requests Table 47 5 Master Interrupts and DMA Requests Flag Description Interrupt DMA Request Low Power Wakeup TDF Data can be written to transmit FIF...

Page 1283: ...ster is busy transmitting receiving data N N N BBF LPI2C master is enabled and activity detected on I2C bus but STOP condition has not been detected and bus idle timeout if enabled has not occurred N...

Page 1284: ...t data underrun receive data overrun or address status overrun when RXCFG 1 This flag can only set when clock stretching is disabled Y N Y AM0F Slave detected address match with ADDR0 field Y N N AM1F...

Page 1285: ...urs following a slave address match It remains asserted until the next slave SCL pin negation 47 4 5 3 Input Trigger The LPI2C input trigger can be selected in place of the LPI2C_HREQ pin to control t...

Page 1286: ...able the TX Data SCL Stall and RX SCL Stall for clock stretching on SCL Enable Slave mode by set LPI2C0_SCR SEN Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1286 NXP Semiconduct...

Page 1287: ...p and VLPS mode provided the clock it is using remains enabled Table 48 1 LPUART Configuration TX FIFO word 10bit RX FIFO word 10bit Single wire mode LPUART0 4 4 Yes LPUART1 4 4 Yes LPUART2 4 4 Yes 48...

Page 1288: ...al Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C FlexIO and LPIT 48 1 3 Inter connectiv...

Page 1289: ...NRZ format Programmable baud rates 13 bit modulo divider with configurable oversampling ratio from 4x to 32x Transmit and receive baud rate can operate asynchronous to the bus clock Baud rate can be c...

Page 1290: ...supporting 1 2 4 8 16 32 64 or 128 idle characters Selectable transmitter output and receiver input polarity Hardware flow control support for request to send RTS and clear to send CTS signals Selecta...

Page 1291: ...TXD Transmit data This pin is normally an output but is an input tristated in single wire mode whenever the transmitter is disabled or transmit direction is configured for receive data I O RXD Receive...

Page 1292: ...TxD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE TE SBK T8 TXDIR Load From LPUARTx_D TXINV BRK13 ASYNCH MODULE CLOCK B...

Page 1293: ...er definition The LPUART includes registers to control baud rate select LPUART options report LPUART status and for transmit receive data Access to an address outside the valid memory map will generat...

Page 1294: ...Baud Rate LPUART1_BAUD 32 RW 0F000004h 4006B014h LPUART Status LPUART1_STAT 32 RW 00C00000h 4006B018h LPUART Control LPUART1_CTRL 32 RW 00000000h 4006B01Ch LPUART Data LPUART1_DATA 32 RW 00001000h 40...

Page 1295: ...r This read only field returns the major version number for the module specification 23 16 MINOR Minor Version Number This read only field returns the minor version number for the module specification...

Page 1296: ...set 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 48 3 1 3 3 Fields Field Function 31 16 Reserved 15 8 RXFIFO Receive FIFO Size The number of words in the receive FIFO is 2 RXFIFO 7 0 TXFIFO Transmit FIFO Size The...

Page 1297: ...2 Reserved 1 RST Software Reset Reset all internal logic and registers except the Global Register Remains set until cleared by software 0 Module is not reset 1 Module is reset 0 Reserved 48 3 1 5 LPUA...

Page 1298: ...served 1 0 TRGSEL Trigger Select Configures the input trigger usage 00 Input trigger is disabled 01 Input trigger is used instead of RXD pin input 10 Input trigger is used instead of CTS_B pin input 1...

Page 1299: ...e 7 bit to 9 bit data characters 1 Receiver and transmitter use 10 bit data characters 28 24 OSR Oversampling Ratio This field configures the oversampling ratio for the receiver between 4x 00011 and 3...

Page 1300: ...ta word when a data one followed by data zero transition is detected This bit should only be changed when the receiver is disabled 0 Resynchronization during received data word is supported 1 Resynchr...

Page 1301: ...e pin has occurred 29 MSBF MSB First Setting this bit reverses the order of the bits that are transmitted and received on the wire This bit does not affect the polarity of the bits the location of the...

Page 1302: ...er detects the beginning of a valid start bit and RAF is cleared automatically when the receiver detects an idle line 0 LPUART receiver idle waiting for a start bit 1 LPUART receiver active RXD input...

Page 1303: ...ne was detected 19 OR Receiver Overrun Flag OR is set when software fails to prevent the receive data register from overflowing with data The OR bit is set immediately after the stop bit has been comp...

Page 1304: ...ntrol CTRL 48 3 1 8 1 Address Register Offset CTRL Base address 18h offset 48 3 1 8 2 Function This read write register controls various optional features of the LPUART system This register should onl...

Page 1305: ...nt character if any before the receiver starts receiving data from the TXD pin 0 TXD pin is an input in single wire mode 1 TXD pin is an output in single wire mode 28 TXINV Transmit Data Inversion Set...

Page 1306: ...to place the LPUART receiver in a standby state RWU automatically clears when an RWU event occurs that is an IDLE event when CTRL WAKE is clear or an address match when CTRL WAKE is set with STAT RWU...

Page 1307: ...the RSRC field determines the source for the receiver shift register input 0 Provided LOOPS is set RSRC is cleared selects internal loop back mode and the LPUART does not use the RXD pin 1 Single wire...

Page 1308: ...s even or odd parity Odd parity means the total number of 1s in the data character including the parity bit is odd Even parity means the total number of 1s in the data character including the parity b...

Page 1309: ...ransmitted instead of the contents in DATA T9 T0 T9 is used to indicate a break character when 0 and a idle character when 1 he contents of DATA T8 T0 should be zero 0 The dataword was received withou...

Page 1310: ...fer 5 4 R4T4 R4T4 Read receive data buffer 4 or write transmit data buffer 4 3 R3T3 R3T3 Read receive data buffer 3 or write transmit data buffer 3 2 R2T2 R2T2 Read receive data buffer 2 or write tran...

Page 1311: ...register when the associated BAUD MAEN bit is clear 15 10 Reserved 9 0 MA1 Match Address 1 The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the a...

Page 1312: ...length These can be configured by selecting the appropriate oversample ratio and pulse width 00 1 OSR 01 2 OSR 10 3 OSR 11 4 OSR 15 8 RTSWATER Receive RTS Configuration Configures the point at which...

Page 1313: ...cter is placed into an empty transmitter data buffer RTS asserts one bit time before the start bit is transmitted RTS deasserts one bit time after all characters in the transmitter data buffer and shi...

Page 1314: ...Buffer Overflow Flag Indicates that more data has been written to the transmit buffer than it can hold This field will assert regardless of the value of TXOFE However an interrupt will be issued to t...

Page 1315: ...9 TXOFE Transmit FIFO Overflow Interrupt Enable When this field is set the TXOF flag generates an interrupt to the host 0 TXOF flag does not generate an interrupt to the host 1 TXOF flag generates an...

Page 1316: ...4 datawords 010 Receive FIFO Buffer depth 8 datawords 011 Receive FIFO Buffer depth 16 datawords 100 Receive FIFO Buffer depth 32 datawords 101 Receive FIFO Buffer depth 64 datawords 110 Receive FIFO...

Page 1317: ...ber of datawords in the transmit FIFO buffer is equal to or less than the value in this register field an interrupt or a DMA request is generated For proper operation the value in TXWATER must be set...

Page 1318: ...l data is available in the transmit data buffer Programs store data into the transmit data buffer by writing to the LPUART data register The central element of the LPUART transmitter is the transmit s...

Page 1319: ...haracter can also be transmitted by writing to the LPUART_DATA register with bit 13 set and the data bits clear This supports transmitting the break character as part of the normal data stream and als...

Page 1320: ...ith characters remaining in the receiver data buffer the character in the shift register is sent and TXD remains in the mark state until CTS_B is reasserted If the clear to send operation is disabled...

Page 1321: ...can be matched to the polarity of the transceiver s driver enable signal TRANSMITTER UART RECEIVER DRIVER RS 485 TRANSCEIVER RECEIVER TXD RTS_B RXD DI DE RO RE_B Y Z A B Figure 48 4 Transceiver driver...

Page 1322: ...UART receiver supports a configurable oversampling rate of between 4 and 32 of the baud rate clock for sampling The receiver starts by taking logic level samples at the oversampling rate times the bau...

Page 1323: ...ceiver to ignore the characters in a message intended for a different receiver During receiver wakeup all receivers evaluate the first character s of each message and as soon as they determine the mes...

Page 1324: ...it data mode and the LPUART_BAUD SBNS bit selects 1 bit or 2 bit stop bit number that determines how many bit times of idle are needed to constitute a full character time 9 to 13 bit times because of...

Page 1325: ...t matches MATCH MA2 when BAUD MAEN2 is set 48 4 3 2 4 Address Match operation Address match operation is enabled when the LPUART_BAUD MAEN1 or LPUART_BAUD MAEN2 bit is set and LPUART_BAUD MATCFG is eq...

Page 1326: ...If both the LPUART_BAUD MAEN1 and LPUART_BAUD MAEN2 bits are negated the receiver operates normally and all data received is transferred to the receive data buffer Idle match operation functions in th...

Page 1327: ...r asserts RTS_B when the number of characters in the receiver data register is not full and has not detected a start bit that will cause the receiver data register to be full It is not affected if STA...

Page 1328: ...r If the next bit is a 0 which arrives late then a low bit is detected according to Low bit detection The value sent to the receiver is changed from 1 to a 0 Then if a noise pulse occurs outside the r...

Page 1329: ...d markers 48 4 4 2 Idle length An idle character is a character where the start bit all data bits and stop bits are in the mark postion The CTRL ILT register can be configured to start detecting an id...

Page 1330: ...o an IR LED and receiving narrow pulses and transforming them to serial bits which are sent to the LPUART The IrDA physical layer specification defines a half duplex infrared communication link for ex...

Page 1331: ...ly generate hardware interrupt requests Transmit data register empty LPUART_STAT TDRE indicates when there is room in the transmit data buffer to write another transmit character to LPUART_DATA If the...

Page 1332: ...ese flags are not set in overrun cases If LPUART_STAT RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun LPUART_STAT O...

Page 1333: ...Information The FlexIO blocks are clocked from a single FlexIO clock that can be selected from OSCCLK SCGIRCLK SCGFIRCLK or SCGFCLK The selected source is controlled by the PCC_FLEXIO register in the...

Page 1334: ...module BUS_CLK Peripheral Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C and LPIT ASYNC...

Page 1335: ...EL 4 bit field to use for starting the counter and or reloading the counter The trigger signal is from the FlexIO module itself which is called internal triggers or from other modules which is called...

Page 1336: ...The FlexIO module is capable of supporting a wide range of protocols including but not limited to UART I2C SPI I2S PWM Waveform generation The following key features are provided Array of 32 bit shift...

Page 1337: ...exIO module supports the chip modes described in the following table Table 49 2 Chip modes supported by the FlexIO module Chip mode FlexIO Operation Run Normal operation Stop Wait Can continue operati...

Page 1338: ...4005_A014 Shifter Error Register FLEXIO_SHIFTERR 32 w1c 0000_0000h 49 3 6 1344 4005_A018 Timer Status Register FLEXIO_TIMSTAT 32 w1c 0000_0000h 49 3 7 1344 4005_A020 Shifter Status Interrupt Enable FL...

Page 1339: ...ster FLEXIO_SHIFTBUFBIS3 32 R W 0000_0000h 49 3 15 1351 4005_A300 Shifter Buffer N Byte Swapped Register FLEXIO_SHIFTBUFBYS0 32 R W 0000_0000h 49 3 16 1351 4005_A304 Shifter Buffer N Byte Swapped Regi...

Page 1340: ...2 32 R W 0000_0000h 49 3 20 1356 4005_A50C Timer Compare N Register FLEXIO_TIMCMP3 32 R W 0000_0000h 49 3 20 1356 49 3 1 Version ID Register FLEXIO_VERID Address 4005_A000h base 0h offset 4005_A000h B...

Page 1341: ...implemented 23 16 PIN Pin Number Number of Pins implemented 15 8 TIMER Timer Number Number of Timers implemented SHIFTER Shifter Number Number of Shifters implemented 49 3 3 FlexIO Control Register F...

Page 1342: ...egister accesses to FlexIO 1 SWRST Software Reset The FlexIO Control Register is not affected by the software reset all other logic in the FlexIO is affected by the software reset and register accesse...

Page 1343: ...curs For SMOD Receive the status flag is set when SHIFTBUF has been loaded with data from Shifter SHIFTBUF is full and the status flag is cleared when SHIFTBUF register is read For SMOD Transmit the s...

Page 1344: ...ue For SMOD Transmit indicates Shifter was ready to load new data from SHIFTBUF before new data had been written into SHIFTBUF SHIFTBUF Underrun For SMOD Match Store indicates a match event occured be...

Page 1345: ...when the 16 bit counter equals zero and decrements this also causes the counter to reload with the value in the compare register 0 Timer Status Flag is clear 1 Timer Status Flag is set 49 3 8 Shifter...

Page 1346: ...abled 1 Shifter Error Flag interrupt enabled 49 3 10 Timer Interrupt Enable Register FLEXIO_TIMIEN Address 4005_A000h base 28h offset 4005_A028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 1347: ...Shifter Status DMA Enable Enables DMA request generation when corresponding SSF is set 0 Shifter Status Flag DMA request is disabled 1 Shifter Status Flag DMA request is enabled 49 3 12 Shifter Contro...

Page 1348: ...d This read only field is reserved and always has the value 0 10 8 PINSEL Shifter Pin Select Selects which pin is used by the Shifter input or output 7 PINPOL Shifter Pin Polarity 0 Pin is active high...

Page 1349: ...Shifter N 1 Output 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 Reserved This field is reserved This read only field is reserved and always has the v...

Page 1350: ...14 Shifter Buffer N Register FLEXIO_SHIFTBUFn Address 4005_A000h base 200h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SHIF...

Page 1351: ...return SHIFTBUF 0 31 49 3 16 Shifter Buffer N Byte Swapped Register FLEXIO_SHIFTBUFBYSn Address 4005_A000h base 300h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1...

Page 1352: ...HIFTBUF 0 7 49 3 18 Timer Control N Register FLEXIO_TIMCTLn Address 4005_A000h base 400h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TRGSEL TRGPOL TRGSRC 0 PIN...

Page 1353: ...This read only field is reserved and always has the value 0 10 8 PINSEL Timer Pin Select Selects which pin is used by the Timer input or output 7 PINPOL Timer Pin Polarity 0 Pin is active high 1 Pin...

Page 1354: ...d only field is reserved and always has the value 0 25 24 TIMOUT Timer Output Configures the initial state of the Timer Output and whether it is affected by the Timer reset 00 Timer output is logic on...

Page 1355: ...IS Timer Disable Configures the condition that causes the Timer to be disabled and stop decrementing 000 Timer never disabled 001 Timer disabled on Timer N 1 disable 010 Timer disabled on Timer compar...

Page 1356: ...has the value 0 49 3 20 Timer Compare N Register FLEXIO_TIMCMPn Address 4005_A000h base 500h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 1357: ...tore_data timer_shift_pos S FXIO_D0 S FXIO_Dn S synchronizer PINSEL SHIFTERi 1 out INSRC PINPOL PINPOL SHIFTERi out FXIO_D0 FXIO_Dn timer_shift_neg TIMPOL PINSEL PINCFG Figure 49 2 Shifter Microarchit...

Page 1358: ...ill clear when the data has been read from the SHIFTBUF register The Shifter Error Flag SHIFTERR SEF and any enabled interrupts will set when an attempt to store data into a full SHIFTBUF register occ...

Page 1359: ...loading shifting and storing of the shift registers the counters load the contents of the compare register and decrement down to zero on the FlexIO clock They can perform generic timer functions such...

Page 1360: ...ft clock after the timer starts decrementing If there is no falling edge on the shift clock before the first rising edge for example when TIMOUT 1 a shifter that is configured to shift on falling edge...

Page 1361: ...l finish A timer enable condition can be detected in the same cycle as a timer disable condition if timer stop bit is disabled or on the first rising edge of the shift clock after the disable conditio...

Page 1362: ...or Shifter Data Input the following synchronization delays occur 1 0 5 1 5 FlexIO clock cycles for external pin 2 1 FlexIO clock cycle for an internally driven pin For timing considerations such as ou...

Page 1363: ...lag as inverted internal trigger source Can support CTS by configuring PINSEL 0x1 for Pin 1 and PINPOL 0x1 SHIFTBUFn Data to transmit Transmit data can be written to SHIFTBUF 7 0 to initiate an 8 bit...

Page 1364: ...request Can support MSB first transfer by reading from SHIFTBUFBIS 7 0 register instead The UART Receiver with RTS configuration uses a 2nd Timer to generate the RTS output The RTS will assert when th...

Page 1365: ...ers and four Pins Either CPHA 0 or CPHA 1 can be supported and transfers can be supported using the DMA controller For CPHA 1 the select can remain asserted for multiple transfers and the timer status...

Page 1366: ...Transmit data can be written to SHIFTBUF use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request Can support MSB first transfer by writing to SHIFTBUFBBS regis...

Page 1367: ...A request Can support MSB first transfer by writing to SHIFTBUFBBS register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBYS use the Shifter Status Flag to indicate when...

Page 1368: ...rst transfer by writing to SHIFTBUFBBS register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBYS use the Shifter Status Flag to indicate when data can be read using inte...

Page 1369: ...fore enabling SCL generation Data transfers can be supported using the DMA controller and the shifter error flag will set on transmit underrun or receive overflow The first timer generates the bit clo...

Page 1370: ...abled logic 0 and stop bit enabled logic 1 SHIFTCTLn 0x0101_0082 Configure transmit using Timer 1 on rising edge of clock with inverted output enable open drain output on Pin 0 SHIFTCFG n 1 0x0000_002...

Page 1371: ...ide of the FlexIO clock frequency and the initial frame sync assertion occurs at the same time as the first bit clock edge The timer uses the start bit to ensure the frame sync is generated one clock...

Page 1372: ...fer by writing to SHIFTBUF register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBIS use the Shifter Status Flag to indicate when data can be read using interrupt or DMA...

Page 1373: ...P n 1 0x0000_003F Configure 32 bit transfers Set TIMCMP 15 0 number of bits x 2 1 TIMCFG n 1 0x0020_3500 Configure enable on pin rising edge with trigger high and disable on compare with trigger low i...

Page 1374: ...lling Interrupt DMA Method Buffer Shifter UART Receive Trigger RX Pin 31 30 29 28 3 2 1 0 31 30 29 28 3 2 1 0 Timer Shift and Store Control FlexIO Clock Reading Buffer Using Polling Interrupt DMA Meth...

Page 1375: ...and Disablement MISO Pin SCK Pin Trigger Timer Output Timer Output FlexIO Clock Load and Shift Control Buffer Shifter Buffer Shifter Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Us...

Page 1376: ...SI Pin SCK Pin Decrement Source Shift and Store Control Load and Shift Control Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt DMA Method Buffer Shifter Buffer...

Page 1377: ...gger Timer Output FlexIO Clock Shift and Store Control Load and Shift Control Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt DMA Method Buffer Shifter Buffer...

Page 1378: ...tput FS Pin Enablement FlexIO Clock Shift and Store Control Load and Shift Control Buffer Shifter Buffer Shifter Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrup...

Page 1379: ...ement FS Pin Shift and Store Control Load and Shift Control Buffer Shifter Buffer Shifter Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt DMA Method RX_DATA Pi...

Page 1380: ...Usage Guide Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1380 NXP Semiconductors...

Page 1381: ...of Message Buffers MB CAN FD feature FlexCAN0 16 MBs No FlexCAN1 16 MBs No 50 1 1 1 Reset value of MDIS bit The CAN_MCR MDIS bit is set after reset Therefore FlexCAN module is disabled following a re...

Page 1382: ...vity is shown in the following diagram CANx CANx_RX CANx_TX CPU DMA INTERRUPT DMA REQ 50 2 Introduction The FlexCAN module is a communication controller implementing the CAN protocol according to the...

Page 1383: ...ce Protocol Engine Tx Arbitration Message Buffers MBs Peripheral Bus Interface Address Data Clocks Interrupts FlexCAN CAN Bus CAN Transceiver Registers Figure 50 1 FlexCAN block diagram 50 2 1 Overvie...

Page 1384: ...matching algorithms The Bus Interface Unit BIU sub module controls the access to and from the internal interface bus in order to establish connection to the CPU and to other blocks Clocks address and...

Page 1385: ...ick Global network time synchronized by a specific message Maskable interrupts Independence from the transmission medium an external transceiver is assumed Short latency time due to an arbitration sch...

Page 1386: ...ield in the Control 1 Register is asserted In this mode FlexCAN performs an internal loop back that can be used for self test operation The bit stream output of the transmitter is internally fed back...

Page 1387: ...ode happens when the Stop mode request is removed or when activity is detected on the CAN bus and the Self Wake Up mechanism is enabled See Stop mode for more information 50 3 FlexCAN signal descripti...

Page 1388: ...ter access and reset information Register Access type Affected by hard reset Affected by soft reset Module Configuration Register CAN_MCR S Yes Yes Control 1 register CAN_CTRL1 S U Yes No Free Running...

Page 1389: ..._ESR1 32 R W See section 50 4 9 1406 4002_4028 Interrupt Masks 1 register CAN0_IMASK1 32 R W 0000_0000h 50 4 10 1412 4002_4030 Interrupt Flags 1 register CAN0_IFLAG1 32 R W 0000_0000h 50 4 11 1412 400...

Page 1390: ...424 4002_48BC Rx Individual Mask Registers CAN0_RXIMR15 32 R W Undefined 50 4 18 1424 4002_5000 Module Configuration Register CAN1_MCR 32 R W See section 50 4 2 1392 4002_5004 Control 1 register CAN1_...

Page 1391: ...sk Registers CAN1_RXIMR5 32 R W Undefined 50 4 18 1424 4002_5898 Rx Individual Mask Registers CAN1_RXIMR6 32 R W Undefined 50 4 18 1424 4002_589C Rx Individual Mask Registers CAN1_RXIMR7 32 R W Undefi...

Page 1392: ...criptions Field Description 31 MDIS Module Disable This bit controls whether FlexCAN is enabled or not When disabled FlexCAN disables the clocks to the CAN Protocol Engine and Controller Host Interfac...

Page 1393: ...only bit indicates that FlexCAN is either in Disable mode Stop mode or Freeze mode It is negated once FlexCAN has exited these modes This bit is not affected by soft reset 0 FlexCAN module is either...

Page 1394: ...SLFWAK Self Wake Up This bit enables the Self Wake Up feature when FlexCAN is in a low power mode other than Disable mode When this feature is enabled the FlexCAN module monitors the bus for wake up...

Page 1395: ...sed either on individual masking and queue or on masking scheme with CAN_RXMGMASK CAN_RX14MASK CAN_RX15MASK and CAN_RXFGMASK This bit can be written in Freeze mode only because it is blocked by hardwa...

Page 1396: ...mode because it is blocked by hardware in other modes 00 Format A One full ID standard and extended per ID Filter Table element 01 Format B Two full standard IDs or two partial 14 bit standard and ex...

Page 1397: ...nd RJW fields of CAN_CTRL1 become read only The contents of this register are not affected by soft reset NOTE The CAN bit variables in CAN_CTRL1 and in CAN_CBT are stored in the same register NOTE The...

Page 1398: ...of Phase Segment 2 in the bit time The valid programmable values are 1 7 This field can be written only in Freeze mode because it is blocked by hardware in other modes Phase Buffer Segment 2 PSEG2 1...

Page 1399: ..._MCR WRNEN bit is asserted 0 Tx Warning Interrupt disabled 1 Tx Warning Interrupt enabled 10 RWRNMSK Rx Warning Interrupt Mask This bit provides a mask for the Rx Warning Interrupt associated with the...

Page 1400: ...er Transmitted First This bit defines the ordering mechanism for Message Buffer transmission When asserted the CAN_MCR LPRIOEN bit does not affect the priority arbitration This bit can be written in F...

Page 1401: ...f any frame is on the CAN bus This captured value is written into the Time Stamp entry in a message buffer after a successful reception or transmission of a message If bit CAN_CTRL1 TSYN is asserted t...

Page 1402: ...x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset CANx_RXMGMASK field descriptions Field Description MG Rx Mailboxes Global Mask Bits These bits mask the Mailbo...

Page 1403: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RX14M W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset CANx_RX14MASK field descriptions Field Descri...

Page 1404: ...TXERRCNT and RXERRCNT counters TXERRCNT and RXERRCNT counters can be written in Freeze mode only The rules for increasing and decreasing these counters are described in the CAN protocol and are compl...

Page 1405: ...a value greater than 127 it is not incremented further even if more errors are detected while being a receiver At the next successful message reception the counter is set to a value between 119 and 12...

Page 1406: ...vicing interrupt requests generated by these bits Read this register to capture all error condition and status bits This action clear the respective bits that were set since the last read access Write...

Page 1407: ...19 18 17 16 R Reserved Reserved 0 Reserved Reserved Reserved 0 ERROVR Reserved BOFFDONEINT SYNCH TWRNINT RWRNINT W w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 50 CAN FlexCAN Kinetis...

Page 1408: ...d only field is reserved and always has the value 0 28 Reserved This field is reserved 27 Reserved This field is reserved 26 Reserved This field is reserved 25 22 Reserved This field is reserved This...

Page 1409: ...is flag is masked CPU must clear this flag before disabling the bit Otherwise it will be set when the WRNEN is set again Writing 0 has no effect This flag is not generated during Bus Off state This bi...

Page 1410: ...l bit 0 No such occurrence 1 A Form Error occurred since last read of this register 10 STFERR Stuffing Error This bit indicates that a Stuffing Error has been detected by the receiver node 0 No such o...

Page 1411: ...errupt This bit is set when FlexCAN enters Bus Off state If the corresponding mask bit in the Control Register 1 CAN_CTRL1 BOFFMSK is set an interrupt is generated to the CPU This bit is cleared by wr...

Page 1412: ...n 31 16 Reserved This field is reserved BUF15TO0M Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB15 to MB0 NOTE Setting or clearing a bit in the...

Page 1413: ...ts are asserted DMA feature for Rx FIFO enabled the function of the 8 least significant interrupt flags BUF7I BUF0I are changed to support the DMA operation BUF7I and BUF6I are not used as well as BUF...

Page 1414: ...nce of MB7 completing transmission reception when MCR RFEN 0 or of Rx FIFO overflow when MCR RFEN 1 1 MB7 completed transmission reception when MCR RFEN 0 or Rx FIFO overflow when MCR RFEN 1 6 BUF6I B...

Page 1415: ...rresponding buffer has no occurrence of successfully completed transmission or reception when MCR RFEN 0 1 The corresponding buffer has successfully completed transmission or reception when MCR RFEN 0...

Page 1416: ...s shown in the following table The maximum selectable number of filters is determined by the chip This field can only be written in Freeze mode as it is blocked by hardware in other modes This field m...

Page 1417: ...odes 18 MRP Mailboxes Reception Priority If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO This bit can be written only in...

Page 1418: ...only field is reserved and always has the value 0 12 ISOCANFDEN ISO CAN FD Enable This field enables the CAN FD protocol according to ISO specification ISO 11898 1 see CAN FD ISO compliance NOTE Flex...

Page 1419: ...number 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 VPS Valid Priority Status This bit indicates whether CAN_ESR2 IMB and CAN_ESR2 LPTM contents ar...

Page 1420: ...50 4 14 CRC Register CANx_CRCR This register provides information about the CRC of transmitted messages This register is updated at the same time the Tx Interrupt Flag is asserted NOTE Refer to CRC se...

Page 1421: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FGM W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset CANx_RXFGMASK field descript...

Page 1422: ...ge See Section Rx FIFO for instructions on reading this register NOTE RXFIR can be written only during memory initialization due to the error code correction ECC feature In every other case the regist...

Page 1423: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANx_CBT field descriptions Field Description 31 BTF Bit Timing Format Enable Enables the use of extended CAN bit timing fields EPRESDIV EPROPSEG EPSEG1 EPSEG2 and E...

Page 1424: ...tten only in Freeze mode because it is blocked by hardware in other modes Phase Buffer Segment 1 EPSEG1 1 Time Quanta Time Quantum one Sclock period EPSEG2 Extended Phase Segment 2 This 5 bit field de...

Page 1425: ...in distinct ways For Mailbox filters see the RXMGMASK register description For Rx FIFO ID Filter Table elements see the RXFGMASK register description 0 The corresponding bit in the filter is don t car...

Page 1426: ...and empty EMPTY FULL When a frame is received successfully after the Move in process the CODE field is automatically updated to FULL 0b0010 FULL MB is full FULL Yes FULL The act of reading the C S wo...

Page 1427: ...See Matching process for details about overrun behavior 0b1010 RANSWER4 A frame was configured to recognize a Remote Request Frame and transmit a Response Frame in return RANSWER TANSWER 0b1110 0 A Re...

Page 1428: ...cess Table 50 6 Message buffer code for Tx buffers CODE Description Tx Code BEFORE tx frame MB RTR Tx Code AFTER successful transmission Comment 0b1000 INACTIVE MB is not active INACTIVE MB does not p...

Page 1429: ...Dominant is not a valid value for transmission in extended format frames IDE ID Extended Bit This field identifies whether the frame format is standard or extended 1 Frame format is extended 0 Frame f...

Page 1430: ...Local priority This 3 bit field is used only when LPRIO_EN bit is set in CAN_MCR and it only makes sense for Tx mailboxes These bits are not transmitted They are appended to the regular ID to define...

Page 1431: ...ilter table configurable from 8 to 40 table elements that specifies filtering criteria for accepting frames into the FIFO Out of reset the ID filter table flexible memory area defaults to 0xE0 and ext...

Page 1432: ...XIDC_1 std ext 23 16 RXIDC_2 std ext 15 8 RXIDC_3 std ext 7 0 Unimplemented or Reserved RTR Remote Frame This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID 1 Re...

Page 1433: ...sage buffer structure The memory corresponding to the first 38 MBs can be configured to support a FIFO reception scheme with a powerful ID filtering mechanism capable of checking incoming frames again...

Page 1434: ...ded via MB_CS RTR c Set Data Length Code in bytes via MB_CS DLC See Table 50 7 for detailed information d Activate the message buffer to transmit the CAN frame by setting MB_CS CODE to 0xC NOTE It is...

Page 1435: ...t number Mailbox and runs toward the higher ones The arbitration process is triggered in the following events From the CRC field of the CAN frame The start point depends on the CAN_CTRL2 TASD field va...

Page 1436: ...itration value of the Mailbox The highest priority Tx Mailbox is the one that has the lowest arbitration value among all Tx Mailboxes If two or more Mailboxes have equivalent arbitration values the Ma...

Page 1437: ...ts content is copied to a hidden auxiliary MB called Tx Serial Message Buffer Tx SMB which has the same structure as a normal MB but is not user accessible This operation is called move out and after...

Page 1438: ...estarted Arbitration process stops in the following situations All Mailboxes were scanned A Tx active Mailbox is found in case of Lowest Buffer feature enabled Arbitration winner inactivation or abort...

Page 1439: ...of the second bit of frame s Identifier field is written into the Mailbox s Time Stamp field 4 The received SRR IDE RTR and DLC fields are stored 5 The CODE field in the Control and Status word is up...

Page 1440: ...lbox may change if the match was due to masking When CAN_MCR SRXDIS bit is asserted FlexCAN will not store frames transmitted by itself in any MB even if it contains a matching Rx Mailbox and no inter...

Page 1441: ...ays looks for a matching MB outside the FIFO region As the frame is being received it is stored in a hidden auxiliary MB called Rx Serial Message Buffer Rx SMB The matching process start point depends...

Page 1442: ...tents with the MB contents regardless the masks 3 no_cmp The Rx SMB contents are not compared with the MB contents 4 cmp_msk Compares the Rx SMB contents with MB contents taking into account the masks...

Page 1443: ...atched Mailbox is found then the matching winner determination is conditioned by the CAN_MCR IRMQ bit If CAN_MCR IRMQ bit is negated the matching winner is the first matched Mailbox If CAN_MCR IRMQ bi...

Page 1444: ...s is a don t care condition 2 Matched in MB None means that the frame has not matched any MB free to receive or non free to receive 3 This is a forbidden condition 4 Matched in MB Free means that the...

Page 1445: ...queue in addition to the full featured FIFO to allow more time for the CPU to service the MBs By programming more than one MB with the same ID received messages are queued into the MBs The CPU can exa...

Page 1446: ...y all of the aforementioned conditions The move in is cancelled and the Rx SMB is able to receive another message if any of the following conditions is satisfied The destination Mailbox is inactivated...

Page 1447: ...ter is in the 124 to 128 range During Bus Idle state During Wait For Bus Idle state The move out process is not atomic Only the CPU has priority to access the memory concurrently out of Bus Idle state...

Page 1448: ...efore the transmission begins internally then the write operation is not blocked therefore the MB is updated and the interrupt flag is set In this way the CPU just needs to read the abort code to make...

Page 1449: ...AN has another data coherence mechanism for the receive process When the CPU reads the Control and Status word of an Rx MB with codes FULL or OVERRUN FlexCAN assumes that the CPU wants to read the who...

Page 1450: ...d and finds out that the BUSY bit is set it should defer accessing the MB until the BUSY bit is negated Note If the BUSY bit is asserted or if the MB is empty then reading the Control and Status word...

Page 1451: ...d messages within the Rx FIFO is increased to 5 from 4 due to the reception of a new one meaning that the Rx FIFO is almost full The flag remains asserted until the CPU clears it The CAN_IFLAG1 BUF7I...

Page 1452: ...rd compatibility with previous versions of the module that did not have the DMA feature The DMA controller can read the received message by reading a Message Buffer structure at the FIFO output port a...

Page 1453: ...is blocked by hardware in other modes This operation does not clear the FIFO IFLAGs consequently the CPU must service all FIFO IFLAGs before execute the clear FIFO task When Rx FIFO is working with D...

Page 1454: ...he receive mailboxes with the CODE field 0b0100 0b0010 or 0b0110 If there is a matching ID then this mailbox will store the remote frame in the same fashion of a data frame No automatic remote respons...

Page 1455: ...eeze modes It can be reset upon a specific frame reception enabling network time synchronization See the TSYN description in Control 1 Register CAN_CTRL1 50 5 8 4 Protocol timing The following figure...

Page 1456: ...waveform A time quantum Tq is the atomic unit of time handled by the CAN engine Tq fCANCLK PRESDIV 1 The bit rate which defines the rate the CAN message is either received or transmitted is given by t...

Page 1457: ...nta in FlexCAN NOTE The bit time defined by the above time segments must not be smaller than 5 time quanta For bit time calculations use an Information Processing Time IPT of 2 which is the value impl...

Page 1458: ...12 4 1 4 6 13 5 1 4 7 14 6 1 4 8 15 7 1 4 9 16 8 1 4 Note The user must ensure the bit time settings are in compliance with the CAN Protocol standard ISO 11898 1 Whenever CAN bit is used as a measure...

Page 1459: ...he CAN frame as shown in the following figures Interm Start Move Move in Window EOF bit 2 Matching Window 26 to 90 CAN bits DATA and or CRC DLC Figure 50 4 Matching and move in time windows CRC Interm...

Page 1460: ...the internal Arbitration process where FlexCAN finds the winner MB for transmission see Arbitration process If the Arbitration ends too early before the first bit of Intermission field then there is a...

Page 1461: ...o little time is reserved for Arbitration the FlexCAN may be not be able to find a winner MB in time to be transmitted with the best chance to win the bus arbitration against external nodes on the CAN...

Page 1462: ...ufficient time to do that the following requirements must be observed The peripheral clock frequency can not be smaller than the oscillator clock frequency For 16 Mailboxes the minimum number of perip...

Page 1463: ...going to Freeze mode Ignores the Rx input pin and drives the Tx pin as recessive Stops the prescaler thus halting all CAN protocol activities Grants write access to the Error Counters Register which i...

Page 1464: ...s to the PE and CHI sub modules Sets the NOTRDY and LPMACK bits in CAN_MCR The Bus Interface Unit continues to operate enabling the CPU to access memory mapped registers except the Rx Mailboxes Global...

Page 1465: ...xCAN entered Stop mode then upon detection of a recessive to dominant transition on the CAN bus FlexCAN sets the WAKINT bit in the CAN_ESR Register and if enabled by the WAKMSK bit in CAN_MCR generate...

Page 1466: ...assumption that the buffer is initialized for either transmission or reception Each of the buffers has an assigned flag bit in the CAN_IFLAG registers The bit is set when the corresponding buffer comp...

Page 1467: ...s to implemented reserved address space results in access error Write access to positions whose bits are all currently read only results in access error If at least one of the bits is not read only th...

Page 1468: ...ts The CAN_MCR SOFTRST bit remains asserted while soft reset is pending so software can poll this bit to know when the reset has completed Also soft reset can not be applied while clocks are shut down...

Page 1469: ...eters EPROPSEG EPSEG1 EPSEG2 ERJW Determine the bit rate by programming the PRESDIV field and optionally the EPRESDIV field Determine the internal arbitration mode LBUF bit Initialize the Message Buff...

Page 1470: ...ive Warning Wake up Wake up 50 7 2 FlexCAN Operation in Low Power Modes The FlexCAN module is operational in VLPR and VLPW modes With the 2 MHz bus clock the fastest supported FlexCAN transfer rate is...

Page 1471: ...ease 3 06 2017 Some major updates after the market launch version rev2 3 1 07 2017 Some minor fixes in the Appendix B Change Summary for rev3 3 2 07 2018 Some major updates after the rev3 4 06 2019 So...

Page 1472: ...Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1472 NXP Semiconductors...

Page 1473: ...troduction chapter changes No substantial content changes B 3 Core Overview chapter changes No substantial content changes B 4 Interrupts chapter changes No substantial content changes B 5 SIM chapter...

Page 1474: ...s B 8 2 MPU module changes No substantial content changes AIPS Lite chapter changes B 9 1 AIPS Lite chip specific changes No substantial content changes B 9 2 AIPS Lite module changes Memory map regis...

Page 1475: ...er changes Minor updates in the table Peripheral bridge slot assignments in the section Peripheral Bridge AIPS Lite Memory Map B 14 LMEM changes No substantial content changes B 15 MSCM changes No sub...

Page 1476: ...nformation of SCG on this device For this device low frequency range 32 kHz 40 kHz medium frequency range 4 MHz 8 MHz high frequency range 8 MHz 40 MHz B 19 2 SCG changes In Fast IRC Configuration Reg...

Page 1477: ...a a4 10 00 97 dd 04 01 00 03 00 04 00 20 64 00 00 00 to 0x5A A4 0C 00 06 5A 04 00 00 02 00 04 00 20 64 00 00 00 In Bootloader Command API section added color to all protocol diagrams In Ping packet se...

Page 1478: ...al content changes B 29 EWM changes No substantial content changes B 30 WDOG changes No substantial content changes B 31 CRC changes No substantial content changes B 32 Debug chapter changes No substa...

Page 1479: ...es B 36 1 GPIO chip specific changes No substantial content changes B 36 2 GPIO changes No substantial content changes ADC chapter changes B 37 1 ADC chip specific changes No substantial content chang...

Page 1480: ...al content changes B 39 DAC changes No substantial content changes B 40 PDB changes No substantial content changes B 41 FTM changes No substantial content changes B 42 LPIT changes Note added in the r...

Page 1481: ...No substantial content changes B 49 FlexIO changes No substantial content changes B 50 FlexCAN module changes Modified Transmit process Added note It is strongly recommended that all the fields in MB...

Page 1482: ...Kinetis KE1xF Sub Family Reference Manual Rev 4 06 2019 1482 NXP Semiconductors...

Page 1483: ...ny vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP the NXP logo NXP SE...

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