
41.5.9 Combine mode
The Combine mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 1, and
• CPWMS = 0
In Combine mode, an even channel (n) and adjacent odd channel (n+1) are combined to
generate a PWM signal in the channel (n) output.
In the Combine mode, the PWM period is determined by (MOD − CNTIN + 0x0001) and
the PWM pulse width (duty cycle) is determined by (|C(n+1)V − C(n)V|).
The CHF bit is set and the channel (n) interrupt is generated (if CHIE = 1) at the channel
(n) match (FTM counter = C(n)V). The channel (n+1) CHF bit is set and the channel (n
+1) interrupt is generated, if channel (n+1) CHIE = 1, at the channel (n+1) match (FTM
counter = C(n+1)V).
If (ELSB:ELSA = 1:0), then the channel (n) output is forced low at the beginning of the
period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n
+1)V). It is forced high at the channel (n) match (FTM counter = C(n)V). See the
following figure.
If (ELSB:ELSA = X:1), then the channel (n) output is forced high at the beginning of the
period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n
+1)V). It is forced low at the channel (n) match (FTM counter = C(n)V). See the
following figure.
In Combine mode, the channel (n) ELSB and channel (n) ELSA bits are not used in the
generation of the channels (n) and (n+1) output. However, if (ELSB:ELSA = 0:0) then
the channel (n) output is not controlled by FTM, and if (channel (n+1) ELSB:ELSA =
0:0) then the channel (n+1) output is not controlled by FTM.
FTM counter
channel (n) match
channel (n) output
with ELSB:ELSA = X:1
with ELSB:ELSA = 1:0
channel (n) output
channel (n+1) match
Figure 41-24. Combine mode
Functional description
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1040
NXP Semiconductors
Summary of Contents for KE1xF Series
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