NXP Semiconductors KE1xF Series, Reference Manual, Page: 1003 / 1483

FTMx_FMS field descriptions (continued)
Field Description
6
WPEN
Write Protection Enable
The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared
when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect.
0 Write protection is disabled. Write protected bits can be written.
1 Write protection is enabled. Write protected bits cannot be written.
5
FAULTIN
Fault Inputs
Represents the logic OR of the enabled fault inputs after their filter (if their filter is enabled) when fault
control is enabled.
0 The logic OR of the enabled fault inputs is 0.
1 The logic OR of the enabled fault inputs is 1.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
FAULTF3
Fault Detection Flag 3
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF3 by reading the FMS register while FAULTF3 is set and then writing a 0 to FAULTF3 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF3 has no effect.
FAULTF3 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF3 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
2
FAULTF2
Fault Detection Flag 2
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF2 by reading the FMS register while FAULTF2 is set and then writing a 0 to FAULTF2 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF2 has no effect.
FAULTF2 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF2 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
1
FAULTF1
Fault Detection Flag 1
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF1 by reading the FMS register while FAULTF1 is set and then writing a 0 to FAULTF1 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF1 has no effect.
FAULTF1 bit is also cleared when FAULTF bit is cleared.
Table continues on the next page...
Chapter 41 FlexTimer Module (FTM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1003