NXP Semiconductors K32 L2A Series, Reference Manual, Page: 99 / 1379

By combining the basic load and store instruction support in the Cortex-M instruction set
architecture with the concept of decorated storage provided by the BME2, the resulting
implementation provides a robust and efficient read-modify-write capability to this class
of ultra low-end microcontrollers. See the
Bit Manipulation Engine Block Guide (BME2)
for a detailed description of BME2 functionality.
4.7 Peripheral bridge (AIPS-Lite) memory map
The peripheral memory map is accessible via 2 slave ports that are on a crossbar.
• AIPS0 is on crossbar AXBS.
• AIPS1 is on crossbar AXBS.
Each AIPSx bridge has 2 regions associated with this space:
• A 128 KB region: partitioned as 32 spaces, each 4 KB in size and reserved for on-
platform peripheral devices. The AIPS controller generates unique module enables
for all 32 spaces.
• A 384 KB region: partitioned as 96 spaces, each 4 KB in size and reserved for off-
platform modules. The AIPS controller generates unique module enables for all 96
spaces.
Modules that are disabled (via their clock gate control bits in the PCC registers) disable
the associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot causes a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral causes a transfer error termination.
4.7.1 AIPS0 Peripheral Slot Assignments
Table 4-3. AIPS0
AIPS0 (no overlap of peripherals)
System 32-bit base address Slot Source Module
0x4000_0000 0 Reserved
0x4000_1000 1 Miscellaneous System Control Module
(MSCM)
0x4000_2000 2 Reserved
0x4000_3000 3 Reserved
0x4000_4000 4 Reserved
0x4000_5000 5 Reserved
Table continues on the next page...
Chapter 4 Memory Map
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 99