NXP Semiconductors K32 L2A Series, Reference Manual, Page: 980 / 1379

37.4.2 HVD interrupt operation
By configuring the HVD circuit for interrupt operation (HVDSC1[HVDIE] set and
HVDSC1[HVDRE] clear), HVDSC1[HVDF] is set and an HVD interrupt request occurs
upon detection of a high voltage condition. HVDSC1[HVDF] is cleared by writing 1 to
HVDSC1[HVDACK].
37.5 I/O retention
When in LLS mode, the I/O pins are held in their input or output state.
Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full
regulation, and releases the logic from state retention mode. The I/O are released
immediately after a wake-up or reset event. In the case of LLS exit via a RESET pin, the
I/O default to their reset state.
When in VLLS modes, the I/O states are held on a wake-up event (with the exception of
wake-up by reset event) until the wake-up has been acknowledged via a write to
REGSC[ACKISO]. In the case of VLLS exit via a RESET pin, the I/O are released and
default to their reset state. In this case, no write to REGSC[ACKISO] is needed.
37.6 Memory map and register descriptions
Details about the PMC registers can be found here.
NOTE
Different portions of PMC registers are reset only by particular
reset types. Each register's description provides details. For
more information about the types of reset on this chip, refer to
the Reset section details.
The PMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
I/O retention
K32 L2A Reference Manual, Rev. 2, 01/2020
980 NXP Semiconductors