NXP Semiconductors K32 L2A Series, Reference Manual, Page: 933 / 1379

36.2.1.7.3 Fields
Field Function
31
PR
This bit shows whether the peripheral is present on this device.
0 - Peripheral is not present.
1 - Peripheral is present.
30
CGC
This read/write bit enables the clock for the peripheral.
0 - Clock disabled
1 - Clock enabled
29
INUSE
This read-only bit indicates the peripheral is being used.
0 - Peripheral is not being used.
1 - Peripheral is being used.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
This read/write bit field is used for peripherals that support various clock selections.
This field can only be written when the CGC bit is 0 (clock disabled). Likewise, if the INUSE flag is set,
this field is locked.
000 - Clock is off (or test clock is enabled).
001 - OSCCLK - System Oscillator Bus Clock.
010 - SCGIRCLK - Slow IRC Clock.
011 - SCGFIRCLK - Fast IRC Clock.
100 - Reserved.
101 - Reserved.
110 - SCGPCLK System PLL clock .
111 - Reserved.
23-4
—
This read-only bit field is reserved and always has the value 0.
3
—
This read-only bit field is reserved and always has the value 0.
2-0
—
This read-only bit field is reserved and always has the value 0.
36.2.1.8 PCC LPTMR0 (PCC_LPTMR0)
36.2.1.8.1 Address
Register Offset
PCC_LPTMR0 4007A0D0h
Chapter 36 Peripheral Clock Control (PCC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 933