NXP Semiconductors K32 L2A Series, Reference Manual, Page: 91 / 1379

3.10.1.1 GPIO instantiation information
The device includes pins PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7
with high current drive capability. These pins can be used to drive LED or power
MOSFETs directly. The high drive capability applies to all functions which are
multiplexed on these pins.
3.10.1.1.1 Pull devices and directions
The pull devices are enabled out of POR only for RESET_b, NMI_b, and the SWD
signals. Coming out of POR:
• RESET_b, NMI_b and SWD_DIO are pulled up.
• SWD_CLK is pulled down.
The pull devices for other pins are not enabled out of POR. They can be enabled by
writing to PORTx_PCRn[PE].
All the pins have controllable pull direction using the PORTx_PCRn[PS] field. All the
pins default to pullup except for SWD_CLK, when enabled.
3.10.1.2 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at
base address 0xF800_0000. It can also be accessed by the core and DMA masters
through the cross bar/AIPS interface address 0x4000_F000. All BME operations to the
GPIO space can be accomplished referencing the address 0x4000_F000.
3.10.2 TSI configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 91