NXP Semiconductors K32 L2A Series, Reference Manual, Page: 824 / 1379

LPUARTx_CTRL field descriptions (continued)
Field Description
20
ILIE
Idle Line Interrupt Enable
ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests.
0 Hardware interrupts from IDLE disabled; use polling.
1 Hardware interrupt requested when IDLE flag is 1.
19
TE
Transmitter Enable
Enables the LPUART transmitter. TE can also be used to queue an idle preamble by clearing and then
setting TE. When TE is cleared, this register bit will read as 1 until the transmitter has completed the
current character and the LPUART_TX pin is tristated.
0 Transmitter disabled.
1 Transmitter enabled.
18
RE
Receiver Enable
Enables the LPUART receiver. When RE is written to 0, this register bit will read as 1 until the receiver
finishes receiving the current character (if any).
0 Receiver disabled.
1 Receiver enabled.
17
RWU
Receiver Wakeup Control
This field can be set to place the LPUART receiver in a standby state. RWU automatically clears when an
RWU event occurs, that is, an IDLE event when CTRL[WAKE] is clear or an address match when
CTRL[WAKE] is set with STAT[RWUID] is clear.
NOTE: RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the channel is currently not idle.
This can be determined by STAT[RAF]. If the flag is set to wake up an IDLE event and the
channel is already idle, it is possible that the LPUART will discard data. This is because the data
must be received or a LIN break detected after an IDLE is detected before IDLE is allowed to be
reasserted.
0 Normal receiver operation.
1 LPUART receiver in standby waiting for wakeup condition.
16
SBK
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 to 13, or 13 to 16 if LPUART_STATBRK13] is set, bit times of logic 0 are queued as long
as SBK is set. Depending on the timing of the set and clear of SBK relative to the information currently
being transmitted, a second break character may be queued before software clears SBK.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
15
MA1IE
Match 1 Interrupt Enable
0 MA1F interrupt disabled
1 MA1F interrupt enabled
14
MA2IE
Match 2 Interrupt Enable
0 MA2F interrupt disabled
1 MA2F interrupt enabled
Table continues on the next page...
Register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
824 NXP Semiconductors