NXP Semiconductors K32 L2A Series, Reference Manual, Page: 808 / 1379

• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
• Hardware flow control support for request to send (RTS) and clear to send (CTS)
signals
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse
width
• Independent FIFO structure for transmit and receive
• Separate configurable watermark for receive and transmit requests
• Option for receiver to assert request after a configurable number of idle
characters if receive FIFO is not empty
31.1.2 Modes of operation
31.1.2.1 Stop mode
The LPUART will remain functional during Stop mode, provided the asynchronous
transmit and receive clock remains enabled. The LPUART can generate an interrupt or
DMA request to cause a wakeup from Stop mode.
31.1.2.2 Wait mode
The LPUART can be configured to Stop in Wait modes, when the DOZEEN bit is set.
The transmitter and receiver will finish transmitting/receiving the current word.
31.1.2.3 Debug mode
The LPUART remains functional in debug mode.
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
808 NXP Semiconductors