NXP Semiconductors K32 L2A Series, Reference Manual, Page: 796 / 1379

Table 30-1. Modes of operation
Modes Description
Run The LPTMR operates normally.
Wait
The LPTMR continues to operate normally and
can be configured to exit the low-power mode by
generating an interrupt request.
Stop
The LPTMR continues to operate normally and
can be configured to exit the low-power mode by
generating an interrupt request.
Low-Leakage
The LPTMR continues to operate normally and
can be configured to exit the low-power mode by
generating an interrupt request.
Debug
The LPTMR operates normally in Pulse Counter
mode, but the counter does not increment in
Time Counter mode.
30.2 LPTMR signal descriptions
Table 30-2. LPTMR signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input pin
30.2.1 Detailed signal descriptions
Table 30-3. LPTMR interface—detailed signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Timing Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
LPTMR signal descriptions
K32 L2A Reference Manual, Rev. 2, 01/2020
796 NXP Semiconductors