NXP Semiconductors K32 L2A Series, Reference Manual, Page: 791 / 1379

The PCSCFG configuration is used to disable LPSPI_PCS[3:2] functions and to use them
for quad-data transfers. This option must be enabled when performing quad-data
transfers.
29.3.3 Slave Mode
LPSPI slave mode uses the same shift register and logic as the master mode, but does not
use the clock configuration register and the transmit command register must remain static
during SPI bus transfers.
29.3.3.1 Transmit and Command FIFO
The transmit command register should be initialized before enabling the LPSPI in slave
mode, although the command register will not update until after the LPSPI is enabled.
Once enabled, the transmit command register should only be changed if the LPSPI is idle.
The following table lists how the command register functions in slave mode.
Table 29-4. LPSPI Command Word in Slave Mode
Field Description
CPOL Configures polarity of the external LPSPI_SCK input.
CPHA Configures clock phase of transfer.
PRESCALE Configures LPSPI functional clock prescaler.
PCS Configures which LPSPI_PCS is used, the polarity of
LPSPI_PCS is static and configured by PCSPOL. If PCSCFG
is set, then PCS[3:2] should not be selected.
LSBF Configures if LSB (bit 0) or MSB (bit 31 for a 32-bit word) is
transmitted/received first.
BYSW Enables byte swap on each 32-bit word when transmitting
and receiving data. Can be useful when interfacing to devices
that organize data as big endean.
CONT When set, only the first FRAMSZ bits will be transmitted/
received by the LPSPI.
CONTC This bit is reserved in slave mode.
RXMSK Masks the receive data and does not store to the receive
FIFO or perform receive data matching. Useful for half-duplex
transfers or to configure which fields are compared during
receive data matching.
Y
TXMSK Masks the transmit data, so that data is not pulled from
transmit FIFO and the output data pin is tristated (unless
configured by OUTCFG). Useful for half-duplex transfers.
Y
WIDTH Configures the number of bits shifted on each LPSPI_SCK
pulse. Single bit transfers support traditional SPI bus transfers
in either half-duplex or full-duplex data formats. Two and four
bit transfers are useful for interfacing to QuadSPI memory
Y
Table continues on the next page...
Chapter 29 Low Power Serial Peripheral Interface (LPSPI)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 791