NXP Semiconductors K32 L2A Series, Reference Manual, Page: 764 / 1379

29.1.3 Block Diagram
LPSPI block diagram
Configuration
Registers
Peripheral
Bus
HREQ
Trigger
Control
Logic
SIN
SOUT
Bus Clock
External Clock
Functional Clock
Clock Domains
Command /
TX
FIFO
RX
FIFO
Shift
Register
SCK
PCS[3:0]
(Everywhere else)
Figure 29-1. Block Diagram
29.1.4 Modes of operation
The LPSPI module supports the chip modes described in the following table.
Table 29-1. Chip modes supported by the LPSPI module
Chip mode LPSPI Operation
Run Normal operation
Stop/Wait Can continue operating if the Doze Enable bit (CR[DOZEN]) is set and the LPSPI
is using an external or internal clock source, which remains operating during stop/
wait modes.
Low Leakage Stop (LLS/VLLS modes) The Doze Enable (CR[DOZEN]) bit is ignored and the LPSPI will wait for the
current transfer to finish any pending operation, before the LPSPI acknowledges
entry into low leakage mode.
Debug (the core is in Debug/Halted
mode) Can continue operating if the Debug Enable bit (CR[DBGEN]) is set.
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
764 NXP Semiconductors