NXP Semiconductors K32 L2A Series, Reference Manual, Page: 763 / 1379

Chapter 29
Low Power Serial Peripheral Interface (LPSPI)
29.1 Introduction
29.1.1 Overview
The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an
efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue
operating in stop modes provided an appropriate clock is available and is designed for
low CPU overhead with DMA offloading of FIFO register accesses.
29.1.2 Features
The LPSPI supports the following features:
• Word size = 32 bits
• Command/transmit FIFO of 4 words.
• Receive FIFO of 4 words.
• Host request input can be used to control the start time of an SPI bus transfer.
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 763