NXP Semiconductors K32 L2A Series, Reference Manual, Page: 74 / 1379

3.7.3.3 Clock Gating
The clock to the VREF module can be turned on or off using the PCC_VREF[CGC] bit
in the PCC module. This bit is cleared after any reset, which disables the clock to the
VREF module to conserve power. Before initializing the VREF module, set
PCC_VREF[CGC] to enable the clock. Before turning off the clock, make sure to disable
the VREF module. For more details, see the clock distribution chapter.
3.7.4 12-bit DAC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Module signals
Register
access
12-bit DAC
Peripheral bus
controller 0
Other
peripherals
Figure 3-9. 12-bit DAC configuration
Table 3-17. Reference links to related information
Topic Related module Reference
Full description 12-bit DAC 12-bit DAC
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.4.1 12-bit DAC instantiation information
This device contains one 12-bit digital-to-analog converter (DAC) with programmable
reference generator output. The DAC includes a 16-word FIFO for DMA support.
VREF
K32 L2A Reference Manual, Rev. 2, 01/2020
74 NXP Semiconductors