NXP Semiconductors K32 L2A Series, Reference Manual, Page: 727 / 1379

LPI2Cx_SCFGR2 field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
FILTSDA
Glitch Filter SDA
Configures the I2C slave digital glitch filters for SDA input, a configuration of 0 will disable the glitch filter.
Glitches equal to or less than FILTSDA cycles long will be filtered out and ignored. The latency through
the glitch filter is equal to 3 cycles and must be configured less than the minimum SCL low or
high period.
The glitch filter cycle count is not affected by the PRESCALE configuration, and is disabled in high speed
mode.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
FILTSCL
Glitch Filter SCL
Configures the I2C slave digital glitch filters for SCL input, a configuration of 0 will disable the glitch filter.
Glitches equal to or less than FILTSCL cycles long will be filtered out and ignored. The latency through the
glitch filter is equal to 3 cycles and must be configured less than the minimum SCL low or high
period.
The glitch filter cycle count is not affected by the PRESCALE configuration, and is disabled in high speed
mode.
15–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13–8
DATAVD
Data Valid Delay
Configures the SDA data valid delay time for the I2C slave equal to 3 cycles. This
data valid delay must be configured to less than the minimum SCL low period.
The I2C slave data valid delay time is not affected by the PRESCALE configuration, and is disabled in
high speed mode.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CLKHOLD Clock Hold Time
Configures the minimum clock hold time for the I2C slave, when clock stretching is enabled. The minimum
hold time is equal to 3 cycles. The I2C slave clock hold time is not affected by the PRESCALE
configuration, and is disabled in high speed mode.
27.2.24 Slave Address Match Register (LPI2Cx_SAMR)
Address: Base a 140h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
ADDR1
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADDR0
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 727