NXP Semiconductors K32 L2A Series, Reference Manual, Page: 694 / 1379

• Command FIFO will wait for idle I2C bus before initiating transfer
• Command FIFO can initiate (repeated) START and STOP conditions and one or
more master-receiver transfers.
• STOP condition can be generated from command FIFO or automatically when the
transmit FIFO is empty.
• Host request input can be used to control the start time of an I2C bus transfer.
• Flexible receive data match can generate interrupt on data match and/or discard
unwanted data.
• Flag and optional interrupt to signal Repeated START condition, STOP condition,
loss of arbitration, unexpected NACK and command word errors.
• Supports configurable bus idle timeout and pin stuck low timeout.
The LPI2C slave supports the following features:
• Separate I2C slave registers to minimize software overhead due to master/slave
switching.
• Support for 7-bit or 10-bit addressing, address range, SMBus alert and general call
address.
• Transmit data register supporting interrupt or DMA requests.
• Receive data register supporting interrupt or DMA requests.
• Software controllable ACK or NACK, with optional clock stretching on ACK/
NACK bit.
• Configurable clock stretching to avoid transmit FIFO underrun and receive FIFO
overrun.
• Flag and optional interrupt at end of packet, STOP condition or bit error detection.
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
694 NXP Semiconductors