NXP Semiconductors K32 L2A Series, Reference Manual, Page: 688 / 1379

LLWU_MF field descriptions (continued)
Field Description
0 Module 3 input was not a wakeup source
1 Module 3 input was a wakeup source
2
MWUF2
Wakeup flag For module 2
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear
the flag, follow the internal peripheral flag clearing mechanism.
0 Module 2 input was not a wakeup source
1 Module 2 input was a wakeup source
1
MWUF1
Wakeup flag For module 1
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear
the flag, follow the internal peripheral flag clearing mechanism.
0 Module 1 input was not a wakeup source
1 Module 1 input was a wakeup source
0
MWUF0
Wakeup flag For module 0
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear
the flag, follow the internal peripheral flag clearing mechanism.
0 Module 0 input was not a wakeup source
1 Module 0 input was a wakeup source
26.3.9 LLWU Pin Filter register (LLWU_FILT)
LLWU_FILT is a control and status register that is used to enable/disable the digital filter
features for an external pin.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4006_1000h base + 30h offset = 4006_1030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FILTF4
FILTE4 FILTSEL4
FILTF3
FILTE3 FILTSEL3
W
w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
688 NXP Semiconductors