NXP Semiconductors K32 L2A Series, Reference Manual, Page: 67 / 1379

Table 3-11. Reference links to related information (continued)
Topic Related module Reference
Clocking Clock distribution
Power management Power management
3.5.7.1 System Register file
This device includes a 32-byte register file that is powered in all power modes.
Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.
Base address of this register file is 0x4007_C000. ( see Table "Peripheral bridge 0 slot
assignment").
Security
3.6.1 CAU Configuration
There is 1 CAU module: CAU0, which is connected to the Core PPB.
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
CAU0
Private Peripheral Bus
Core
Figure 3-5. CAU configuration
3.6.1.1 CAU Overview
The CAU provides security encrypt/decrypt acceleration to allow users to share secure
data with external devices via a serial communication port (such as an LPUART module).
3.6
Chapter 3 Chip Configuration
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 67