NXP Semiconductors K32 L2A Series, Reference Manual, Page: 666 / 1379

• Input sources may be external pins or from internal peripherals capable of running in
LLS or VLLS. See the chip configuration information for wakeup input sources for
this device.
• External pin wake-up inputs, each of which is programmable as falling-edge, rising-
edge, or any change
• Wake-up inputs that are activated after MCU enters a low-leakage power mode
• Optional digital filters provided to qualify an external pin detect. Note that when the
LPO clock is disabled, the filters are disabled and bypassed.
26.1.2 Modes of operation
The LLWU module becomes functional on entry into a low-leakage power mode. After
recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the
LLWU continues to detect wake-up events until the user has acknowledged the wake-up
via a write to PMC_REGSC[ACKISO].
26.1.2.1 LLS mode
Wake-up events due to external pin inputs (LLWU_Px) and internal module interrupt
inputs (LLWU_MxIF) result in an interrupt flow when exiting LLS. Wake-up events due
to internal module DMA requests (LLWU_MxDF) allow the system to temporarily exit
LLS with the CPU clock disabled, allowing the DMA request to be serviced. When the
module DMA request negates, the system will re-enter LLS.
NOTE
The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit Stop mode on an LLS recovery.
26.1.2.2 VLLS modes
All wakeup and reset events result in VLLS exit via a reset flow.
26.1.2.3 Non-low leakage modes
The LLWU is not active in all non-low leakage modes where detection and control logic
are in a static state. The LLWU registers are accessible in non-low leakage modes and are
available for configuring and reading status when bus transactions are possible.
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
666 NXP Semiconductors