NXP Semiconductors K32 L2A Series, Reference Manual, Page: 660 / 1379

INTMUXx_CHn_CSR field descriptions
Field Description
31
IRQP
Channel Interrupt Request Pending
This bit is available for polling purposes and represents the channel output.
0 No interrupt is pending.
1 The interrupt output of this channel is pending.
30–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
CHIN
Channel Instance Number
These bits represent the instance number of this channel.
N Channel N
7–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–4
IRQN
Channel Input Number
These bits represent the interrupt input number of this channel.
00 32 interrupt inputs
01 Reserved
10 Reserved
11 Reserved
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
AND
Logic AND
This bit used to Logic AND or Logic OR all enabled interrupt inputs of this channel and generate the
interrput output of this channel.
0 Logic OR all enabled interrupt inputs.
1 Logic AND all enabled interrupt inputs.
0
RST
Software Reset
This bit is used to software reset this channel. This bit always reads as 0.
0 No operation.
1 Perform a software reset on this channel.
25.2.2 Channel n Vector Number Register (INTMUXx_CHn_VEC)
Address: 4002_4000h base + 4h (64d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 VECN 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory Map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
660 NXP Semiconductors