NXP Semiconductors K32 L2A Series, Reference Manual, Page: 66 / 1379

Signal
multiplexing
Module signals
Register
access
Peripheral Clock
Control (PCC)
Peripheral bus
controller 1
Figure 3-3. PCC configuration
3.5.6.1 Overview
The device deploys two Peripheral Clock Control modules that allow clock gating, and
clock source selection to each peripheral. Each AIPS bridge has its own corresponding
PCC module.
In addition to this clock, there are optional peripheral clock sources that may be
asynchronous to the CPU/Platform clock: SCGIRCLK, SCGFIRCLK, SCGPCLK,
SCGFCLK, LPO, OSCCLK, SCGSPCLK.
3.5.7 System Register File Configuration
This section summarizes how the module has been configured in the chip.
Register file
Peripheral
bridge 0
Register
access
Figure 3-4. System Register file configuration
Table 3-11. Reference links to related information
Topic Related module Reference
Full description Register file Register file
System memory map System memory map
Table continues on the next page...
Watchdog (WDOG)
K32 L2A Reference Manual, Rev. 2, 01/2020
66 NXP Semiconductors