NXP Semiconductors K32 L2A Series, Reference Manual, Page: 65 / 1379

Register file
Peripheral
bridge 0
Register
access
Figure 3-2. System Register file configuration
Table 3-10. Reference links to related information
Topic Related module Reference
Full description Register file Register file
System memory map System memory map
Clocking Clock distribution
Power management Power management
3.5.5.1 System Register file
This device includes a 32-byte register file that is powered in all power modes.
Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.
Base address of this register file is 0x4007_C000. ( see Table "Peripheral bridge 0 slot
assignment").
3.5.6 Peripheral Clock Control (PCC) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 65