NXP Semiconductors K32 L2A Series, Reference Manual, Page: 64 / 1379

Table 3-9. DMA request sources - MUX0 (continued)
Source No Source module Source description Async DMA capable
45 Reserved — —
46 Reserved — —
47 PortA Port Control module Yes
48 PortB Port Control module Yes
49 PortC Port Control module Yes
50 PortD Port Control Module Yes
51 PortE Port Control module Yes
52 ADC0 Conversion complete Yes
53 Reserved — —
54 DAC0 Digital-to-Analog Converter Yes
55 Reserved — —
56 CMP0 Comparator Yes
57 CMP1 Comparator Yes
58 Reserved — —
59 Reserved — —
60 TSI Touch Sensor Interface Yes
61 LPTMR0 Low Power Timer 0 Yes
62 LPTMR1 Low Power Timer 1 Yes
63 DMA MUX Always enabled
Watchdog (WDOG)
3.5.4.1 WDOG clocks
The multiple clock inputs for the WDOG are:
• 1 kHz clock
• bus clock
• 8 MHz or 2 MHz internal reference clock
• external crystal
3.5.5 System Register File Configuration
This section summarizes how the module has been configured in the chip.
3.5.4
Watchdog (WDOG)
K32 L2A Reference Manual, Rev. 2, 01/2020
64 NXP Semiconductors