NXP Semiconductors K32 L2A Series, Reference Manual, Page: 589 / 1379

1. Configure FlexIO with 1-beat write configuration
2. Configure GPIO to assert nCS, RS pins (and deassert RDWR pin for 68K)
3. Write register index data to SHIFTBUF0[15:0]
4. Configure GPIO to deassert RS pin (and assert RDWR pin for 68K data read)
5. Configure FlexIO with desired read or write configuration (e.g. 1 or 16-beats)
6. Use the Shifter Status Flag to trigger interrupt or DMA driven data transfers to/from
SHIFTBUF registers
7. Configure GPIO to deassert nCS pin
22.4.10 Low Power State Machine
The configuration below details a hypothetical state machine example to illustrate the
flexibility allowed when using Shifter state mode.
In this example, FlexIO waits for the FXIO_D[2] pin to assert and then drives a
complementary square wave output at a frequency of FLEXIO_CLK/131072 on the
FXIO_D[1:0] pins while the comparator output is asserted (assumes comparator is
connected to external trigger 15, see Chip Configuration chapter for actual FlexIO trigger
mappings). Throughout this operation, the CPU can be kept in a STOP/VLPS mode, by
clearing the CTRL[DOZEN] bit and ensuring the FLEXIO_CLK is enabled. The state
diagram below shows the states and transitions implemented by this example.
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 589