NXP Semiconductors K32 L2A Series, Reference Manual, Page: 586 / 1379

Table 22-13. I2S Slave Configuration (continued)
Register Value Comments
TIMCMP(n+1) 0x0000_003F Configure 32-bit transfers. Set
TIMCMP[15:0] = (number of bits x 2) - 1.
TIMCFG(n+1) 0x0020_3500 Configure enable on pin rising edge with
trigger high and disable on compare with
trigger low, initial clock state is logic 0
and decrement on pin input.
TIMCTL(n+1) 0x0340_0203 Configure 16-bit counter using Pin 2
input (bit clock), with Timer 0 output as
the trigger.
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be
written using interrupt or DMA request.
Can support LSB first transfer by writing
to SHIFTBUF register instead.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support LSB first transfer by reading
from SHIFTBUF register instead.
22.4.8 Camera Interface
Camera Interface can be supported using one Timer, one or more Shifters and multiple
Pins. Multiple transfers can be supported using DMA controller.
The example below describes FlexIO configuration for interfacing to an 8-bit CMOS
sensor with PCLK, VSYNC, HREF and D[7:0] outputs. The example uses a 128-bit
buffer to capture 16-pixels of image data before interrupt or DMA transfer, however a
bigger or smaller buffer may be used depending on system DMA performance and
FlexIO resource usage by other applications. Note that additional timers may be used to
track number of pixels per row and number of rows per frame or HREF/VSYNC may be
assigned as GPIO interrupts for software tracking.
Table 22-14. Camera Interface Configuration for 8-bit CMOS sensor
Register Value Comments
SHIFTCFGn...n+2
1
0x0007_0100 Configure 8-bit parallel shift in from
adjacent shifter.
SH3 0x0007_0000 Configure 8-bit parallel shift in from pins
FXIO_D[7:0] (D[7:0]).
SHIFTCTLn...n+3 0x0080_0001 Configure receive using Timer 0 on
negedge of clock.
Table continues on the next page...
Application Information
K32 L2A Reference Manual, Rev. 2, 01/2020
586 NXP Semiconductors