NXP Semiconductors K32 L2A Series, Reference Manual, Page: 585 / 1379

Table 22-12. I2S Master Configuration (continued)
Register Value Comments
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support LSB first transfer by reading
from SHIFTBUF register instead.
22.4.7 I2S Slave
I2S slave mode can be supported using two Timers, two Shifters and four Pins (for single
transmit and single receive, other combinations of transmit and receive are possible).
The transmit data must be written to the transmit buffer register before the external frame
sync asserts, otherwise the shifter error flag will be set.
Due to synchronization delays, the output valid time for the serial output data is 2.5
FlexIO clock cycles, so the maximum baud rate is divide by 6 of the FlexIO clock
frequency.
The output valid time of I2S slave is max 2.5 cycles because there is a maximum 1.5
cycle delay on the clock synchronization plus 1 cycle to output the data
Table 22-13. I2S Slave Configuration
Register Value Comments
SHIFTCFGn 0x0000_0000 Start and stop bit disabled.
SHIFTCTLn 0x0103_0002 Configure transmit using Timer 1 on
rising edge of shift clock with output data
on Pin 0.
SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.
SHIFTCTL(n+1) 0x0180_0101 Configure receive using Timer 1 on
falling edge of shift clock with input data
on Pin 1.
TIMCMPn 0x0000_007D Configure two 32-bit transfers per frame.
Set TIMCMP[15:0] = (number of bits x 4)
- 3.
TIMCFGn 0x0030_2400 Configure enable on pin rising edge
(inverted frame sync) and disable on
compare, initial clock state is logic 1 and
decrement on trigger input (bit clock).
TIMCTLn 0x0440_0383 Configure 16-bit counter using inverted
Pin 3 input (frame sync), with Pin 2 input
(bit clock) as the trigger.
Table continues on the next page...
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 585