NXP Semiconductors K32 L2A Series, Reference Manual, Page: 580 / 1379

Table 22-8. SPI Master (CPHA=1) Configuration (continued)
Register Value Comments
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBYS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support MSB first transfer by reading
from SHIFTBUFBIS register instead.
22.4.4 SPI Slave
SPI slave mode can be supported using one Timer, two Shifters and four Pins. Either
CPHA=0 or CPHA=1 can be supported and transfers can be supported using the DMA
controller. For CPHA=1, the select can remain asserted for multiple transfers and the
timer status flag can be used to indicate the end of the transfer.
The transmit data must be written to the transmit buffer register before the external slave
select asserts, otherwise the shifter error flag will be set.
Due to synchronization delays, the output valid time for the serial output data is 2.5
FlexIO clock cycles, so the maximum baud rate is divide by 6 of the FlexIO clock
frequency.
Table 22-9. SPI Slave (CPHA=0) Configuration
Register Value Comments
SHIFTCFGn 0x0000_0000 Start and stop bit disabled.
SHIFTCTLn 0x0083_0002 Configure transmit using Timer 0 on
falling edge of shift clock with output
data on Pin 0.
SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.
SHIFTCTL(n+1) 0x0000_0101 Configure receive using Timer 0 on
rising edge of shift clock with input data
on Pin 1.
TIMCMPn 0x0000_003F Configure 32-bit transfer. Set
TIMCMP[15:0] = (number of bits x 2) - 1.
TIMCFGn 0x0120_6000 Configure enable on trigger rising edge,
initial clock state is logic 0 and
decrement on pin input.
TIMCTLn 0x06C0_0203 Configure 16-bit counter using Pin 2
input (shift clock), with Pin 3 input (slave
select) as the inverted trigger.
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUF, use the Shifter Status Flag
to indicate when data can be written
using interrupt or DMA request. Can
Table continues on the next page...
Application Information
K32 L2A Reference Manual, Rev. 2, 01/2020
580 NXP Semiconductors