NXP Semiconductors K32 L2A Series, Reference Manual, Page: 571 / 1379

SHIFTCFG[PWIDTH] will control the number of delay stages introduced by the internal
shifter input (SHIFTERi[0]). For example, when configured for 1-bit shift (PWIDTH=0),
the internal shifter will introduce a 32 Shift clock delay before passing its input (selected
by SHIFTCTL[PINSEL]) to the look-up table. When configured for 32-bit shift
(PWIDTH=16...31), the internal shifter will introduce a 1 Shift clock delay to its input.
The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requests
will set whenever the output pin allocated to the logic look-up table has a value of 1 (after
being synchronized to the FlexIO clock). The flag will clear when the output pin has a
value of 0. This also allows the SSF flag to be used as a trigger to a Timer if desired.
The Shifter Error Flag (SHIFTERR[SEF]) and any enabled interrupts will set when the
output pin allocated to the logic look-up table has a value of 1. The flag can be cleared by
writing it with logic 1.
22.3.2 Timer operation
The FlexIO 16-bit timers control the loading, shifting and storing of the shift registers,
the counters load the contents of the compare register and decrement down to zero on the
FlexIO clock. They can perform generic timer functions such as generating a clock or
select output or a PWM waveform. Timers can be configured to enable in response to a
trigger, pin or shifter condition; decrement always or only on a trigger or pin edge; reset
in response to a trigger or pin condition; and disable on a trigger or pin condition or on a
timer compare. Timers can optionally include a start condition and/or stop condition.
Each timer operates independently, although a timer can be configured to enable or
disable at the same time as the previous timer (eg: timer1 can enable or disable at the
same time as timer 0) and a timer output can be used to trigger any other timer. The
trigger used by each timer is configured independently and can be configured to be a
timer output, shifter status flag, pin input or an external trigger input (refer to the chip
configuration section for details on the external trigger connections). The trigger
configuration is separate from the pin configuration, which can be configured for input,
output data or output enable.
The Timer Configuration Register (TIMCFGn) should be configured before setting the
Timer Mode (TIMOD). Once the TIMOD is configured for the desired mode, when the
condition configured by timer enable (TIMENA) is detected then the following events
occur.
• Timer counter will load the current value of the Compare Register and start
decrementing as configured by TIMDEC.
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 571