NXP Semiconductors K32 L2A Series, Reference Manual, Page: 521 / 1379

programmable guard time in the GETU register. However, the time between the
last byte in the transmit FIFO, and the next transmitted byte can be largely
affected by software response time to the transmit interrupts. The EMV SIM
transmitter provides a Transmit FIFO threshold (TDTF) interrupt to signal the
system when the expected number of characters have been transmitted from the
transmit FIFO. The minimum CWT is achieved only if the software can respond
to the TDTF interrupt and write new data to the transmit FIFO before the last
character in the Transmit FIFO has been sent.
• Block Waiting Time
• The block waiting time (BWT) is defined as the maximum time between the start
bits of the last character of a transmitted block and the first character of the next
received block. The value of BWT is always greater than 1800 ETU. The EMV
SIM transmitter provides two General Purpose Counter(s) either of which can be
used to track the BWT. The BWT is purely determined by software response
time to the transmit interrupts.
• Block Guard Time
• The block guard time (BGT) is defined as the minimum delay between the start
bits of the last character of a transmitted block and the first character of the next
received block. The value of BGT is 22 ETU. The EMV SIM module supports
the BGT by providing the ability to generate an interrupt when the last byte is
received, and transmitting within 2 ETU after the XMT_EN bit is set. The BGT
will be determined by the speed at which the software can react to an interrupt
and enable the transmitter.
• Error Detection Code
• “T=1” cards can specify LRC or CRC error detection codes to be used. The
EMV SIM module provides hardware support for both the LRC and CRC
operation.
21.6.5 LRC and CRC
21.6.5.1 LRC Block
The EMV SIM module provides an 8-bit Linear Redundancy Check (LRC) generator /
checker. The block is provided for use with T=1 Smart Cards that support LRC. This
block can be enabled through the LRC_EN bit in the CNTL register. This block performs
an 8-bit exclusive-OR on all received or transmitted characters. At the end of the
reception of a block of characters, the result is expected to be 00. If so, the LRC_OK bit
is set in the RX_STATUS register. During transmission, the LRC block Exclusive-ORs
Chapter 21 Smart Card Interface Module (EMV SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 521