NXP Semiconductors K32 L2A Series, Reference Manual, Page: 515 / 1379

• SRST bit in PCSR register
• VCC_EN bit in PCSR register
• XMT_EN and RCV_EN bits in CTRL register
21.6.3 EMV SIM Receiver
The EMV SIM Receiver is designed to receive all message bytes and store valid bytes
into the receive FIFO. It performs checks on the incoming messages and indicates the
transmitter to enable NACK insertion for each message. In addition, the receiver
automatically detects NACKs received when the transmitter is sending out message
bytes.
21.6.3.1 Data Sampling
The incoming data is internally synchronized and sampled using a 16x oversampled
clock, called the EMV SIM logic clock. The frequency of this clock is 16 times the ETU
Clock (1/ETU Period). The whole receiver works on this EMV SIM logic clock.
21.6.3.2 Initial Character Detection
The EMV SIM module supports the detection of the Initial Character and determine the
data format when it is placed in the initial character mode by setting the ICM bit in CTRL
register. When placed in this mode, the EMV SIM module samples in the input line and
waits for one of the initial characters to be detected. Once detected, the ICM bit is cleared
and the data format bit, IC bit, is set to appropriate value depending on the data format
detected using the initial character.
The two possible data formats are inverse convention and direct convention. Figures
below illustrate the differences between the two formats. Essentially, inverse convention
differs from direct convention in that the order of the bits is flipped (i.e. MSB for LSB)
and the data bits and parity bit are logically inverted. When receiving inverse convention
data, the transformation of the data back to direct convention format is done in hardware,
including the inversion of the data and parity bits.
Chapter 21 Smart Card Interface Module (EMV SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 515