NXP Semiconductors K32 L2A Series, Reference Manual, Page: 399 / 1379

As such, configuration of the DMAMUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in
Enabling and
configuring sources is followed, the configuration of the DMAMUX may be changed
during the normal operation of the system.
Functionally, the DMAMUX channels may be divided into two classes:
• Channels that implement the normal routing functionality plus periodic triggering
capability
• Channels that implement only the normal routing functionality
19.4.1 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism
to transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention.
The trigger is generated by the periodic interrupt timer (LPIT); as such, the configuration
of the periodic triggering interval is done via configuration registers in the LPIT. See the
section on periodic interrupt timer for more information on this topic.
Note
Because of the dynamic nature of the system (due to DMA
channel priorities, bus arbitration, interrupt service routine
lengths, etc.), the number of clock cycles between a trigger and
the actual DMA transfer cannot be guaranteed.
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 399