NXP Semiconductors K32 L2A Series, Reference Manual, Page: 390 / 1379

DACx_C0 field descriptions (continued)
Field Description
0 The DAC system is disabled.
1 The DAC system is enabled.
6
DACRFS
DAC Reference Select
0 The DAC selects DACREF_1 as the reference voltage.
1 The DAC selects DACREF_2 as the reference voltage.
5
DACTRGSEL
DAC Trigger Select
0 The DAC hardware trigger is selected.
1 The DAC software trigger is selected.
4
DACSWTRG
DAC Software Trigger
Active high. This is a write-only field, which always reads 0. If DAC software trigger is selected and buffer
is enabled, writing 1 to this field will advance the buffer read pointer once.
0 The DAC soft trigger is not valid.
1 The DAC soft trigger is valid.
3
LPEN
DAC Low Power Control
NOTE: See the 12-bit DAC electrical characteristics of the device data sheet for details on the impact of
the modes below.
0 High-Power mode
1 Low-Power mode
2
DACBWIEN
DAC Buffer Watermark Interrupt Enable
0 The DAC buffer watermark interrupt is disabled.
1 The DAC buffer watermark interrupt is enabled.
1
DACBTIEN
DAC Buffer Read Pointer Top Flag Interrupt Enable
0 The DAC buffer read pointer top flag interrupt is disabled.
1 The DAC buffer read pointer top flag interrupt is enabled.
0
DACBBIEN
DAC Buffer Read Pointer Bottom Flag Interrupt Enable
0 The DAC buffer read pointer bottom flag interrupt is disabled.
1 The DAC buffer read pointer bottom flag interrupt is enabled.
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
390 NXP Semiconductors