NXP Semiconductors K32 L2A Series, Reference Manual, Page: 376 / 1379

WAS
Polynomial
MUX
CRC Engine
NOT
Logic
Reverse
Logic
Reverse
Logic
[31:24]
[23:16]
[15:8]
[7:0]
CRC Data
Seed
TOT TOTR FXOR
Combine
Logic
TCRC
[31:24]
[23:16]
[15:8]
[7:0]
16-/32-bit Select
CRC Data Register
CRC Polynomial
Register
[31:24]
[23:16]
[15:8]
[7:0]
CRC Data Register
Checksum
Data
Figure 17-1. Programmable cyclic redundancy check (CRC) block diagram
17.1.3 Modes of operation
Various MCU modes affect the CRC module's functionality.
17.1.3.1 Run mode
This is the basic mode of operation.
17.1.3.2 Low-power modes (Wait or Stop)
Any CRC calculation in progress stops when the MCU enters a low-power mode that
disables the module clock. It resumes after the clock is enabled or via the system reset for
exiting the low-power mode. Clock gating for this module is dependent on the MCU.
17.2 Memory map and register descriptions
CRC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_8000 CRC Data register (CRC_DATA) 32 R/W FFFF_FFFFh 17.2.1/377
4007_8004 CRC Polynomial register (CRC_GPOLY) 32 R/W 0000_1021h 17.2.2/378
4007_8008 CRC Control register (CRC_CTRL) 32 R/W 0000_0000h 17.2.3/378
Memory map and register descriptions
K32 L2A Reference Manual, Rev. 2, 01/2020
376 NXP Semiconductors