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CMPx_CR1 field descriptions (continued)
Field
Description
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set
and WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved
and may change in future implementations.
0
Windowing mode is not selected.
1
Windowing mode is selected.
5
TRIGM
Trigger Mode Enable
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the
CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled.
CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC
in order to generate a triggered compare.
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource
trigger is received.
See the chip configuration for details about the external timer resource.
0
Trigger mode is disabled.
1
Trigger mode is enabled.
4
PMODE
Power Mode Select
See the electrical specifications table in the device Data Sheet for details.
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay
and lower current consumption.
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay
and higher current consumption.
3
INV
Comparator INVERT
Allows selection of the polarity of the analog comparator function. It is also driven to the COUT output, on
both the device pin and as SCR[COUT], when OPE=0.
0
Does not invert the comparator output.
1
Inverts the comparator output.
2
COS
Comparator Output Select
0
Set the filtered comparator output (CMPO) to equal COUT.
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
1
OPE
Comparator Output Pin Enable
0
CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin,
this field has no effect.
1
CMPO is available on the associated CMPO output pin.
The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator
owns the pin. If the comparator does not own the field, this bit has no effect.
0
EN
Comparator Module Enable
Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and
consumes no power. When the user selects the same input from analog mux to the positive and negative
port, the comparator is disabled automatically.
Table continues on the next page...
Memory map/register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
352
NXP Semiconductors
Summary of Contents for K32 L2A Series
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Page 122: ...Flash Memory Clock K32 L2A Reference Manual Rev 2 01 2020 122 NXP Semiconductors...
Page 158: ...Debug and security K32 L2A Reference Manual Rev 2 01 2020 158 NXP Semiconductors...
Page 174: ...Module Signal Description Tables K32 L2A Reference Manual Rev 2 01 2020 174 NXP Semiconductors...
Page 246: ...Application information K32 L2A Reference Manual Rev 2 01 2020 246 NXP Semiconductors...
Page 374: ...CMP Trigger Mode K32 L2A Reference Manual Rev 2 01 2020 374 NXP Semiconductors...
Page 384: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 384 NXP Semiconductors...
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