NXP Semiconductors K32 L2A Series, Reference Manual, Page: 230 / 1379

448 MB space at addresses 0x4400_0000–0x5FFF_FFFF; these bits are stripped out of
the actual address sent to the peripheral bus controller and used by the BME to define and
control its operation.
13.1.1 Features
The key features of the BME2 include:
• Lightweight implementation of decorated storage for selected address spaces
• Additional access semantics encoded into the reference address
• Resides between crossbar switch slave port(s) and their associated peripheral bridge
bus controller(s)
• Two-stage pipeline design matching the AHB system bus protocol
• Combinationally passes non-decorated accesses to peripheral bridge bus controllers
• Conversion of decorated loads and stores from processor core into atomic read-
modify-writes
• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit
operations
• Decorated stores support bit field inserts, logical AND, OR, and XOR operations
• Support for byte, halfword and word-sized decorated operations
• Supports minimum signal toggling on AHB output bus to reduce power dissipation
13.1.2 Modes of operation
The BME modules do not support any special modes of operation. As memory-mapped
devices located on crossbar slave AHB system bus ports, BME responds strictly on the
basis of memory addresses for accesses to the SRAM_U and AIPS controllers.
All functionality associated with the BME modules reside in the core platform's clock
domain; this includes their connections with the crossbar slave ports, SRAM_U, and the
AIPS controllers.
13.2 Memory map and register definition
The BME module provides a memory-mapped capability and does not include any
programming model registers.
The exact set of functions supported by the BME are detailed in the Functional
description .
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
230 NXP Semiconductors