NXP Semiconductors K32 L2A Series, Reference Manual, Page: 203 / 1379

11.4.2 Voltage reference selection
The ADC can be configured to accept one of the two voltage reference pairs as the
reference voltage (V
REFSH
and V
REFSL
) used for conversions.
Each pair contains a positive reference that must be between the minimum Ref Voltage
High and V
DDA
, and a ground reference that must be at the same potential as V
SSA
. The
two pairs are external (V
REFH
and V
REFL
) and alternate (V
ALTH
and V
ALTL
). These
voltage references are selected using SC2[REFSEL]. The alternate (V
ALTH
and V
ALTL
)
voltage reference pair may select additional external pins or internal sources depending
on MCU configuration. See the chip configuration information on the voltage references
specific to this MCU.
11.4.3 Hardware trigger and channel selects
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT,
that is enabled when SC2[ADTRG] is set and a hardware trigger select event,
ADHWTSn, has occurred.
This source is not available on all MCUs. See the chip-specific ADC information for
information on the ADHWT source and the ADHWTSn configurations specific to this
MCU.
When an ADHWT source is available and hardware trigger is enabled, that is
SC2[ADTRG]=1, a conversion is initiated on the rising-edge of ADHWT after a
hardware trigger select event, that is, ADHWTSn, has occurred. If a conversion is in
progress when a rising-edge of a trigger occurs, the rising-edge is ignored. In continuous
convert configuration, only the initial rising-edge to launch continuous conversions is
observed, and until conversion is aborted, the ADC continues to do conversions on the
same SCn register that initiated the conversion. The hardware trigger function operates in
conjunction with any of the conversion modes and configurations.
The hardware trigger select event, ADHWTSn, must be set prior to the receipt of the
ADHWT signal. If these conditions are not met, the converter may ignore the trigger or
use the incorrect configuration. If a hardware trigger select event is asserted during a
conversion, it must stay asserted until the end of current conversion and remain set until
the receipt of the ADHWT signal to trigger a new conversion. The channel and status
fields selected for the conversion depend on the active trigger select signal:
• ADHWTSA active selects SC1A.
• ADHWTSn active selects SC1n.
Chapter 11 Analog-to-Digital Converter (ADC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 203