NXP Semiconductors K32 L2A Series, Reference Manual, Page: 151 / 1379

• The MDM-AP supports flash programming/erase, debug options in the various stop
modes, flash security, and resetting the Core. See the MDM-AP registers.
• The AHB-APx module connects to the M0+ core via a private AHB bus, allowing
the debugger tool to set up watchpoints, breakpoints, instruction stepping, halting/
starting CPU execution.
• Tracing of code execution deploys Arm’s Micro Trace Buffer (MTB) module, which
connects to the main AHB-Lite interface and provides the interface to the RAM.
Table 9-2. Debug Access Ports and AP numbers
Debug Access Ports AP Number
Core0 AHB-AP AP 0
MDM-AP AP 1
9.4 SWD status and control registers
Through the Arm Debug Access Port (DAP), the debugger has access to the status and
control elements, implemented as registers on the DAP bus as shown in the figure found
here.
These registers provide additional control and status for low power mode recovery and
typical run-control scenarios. The status register bits also provide a means for the
debugger to get updated status of the core, without having to initiate a bus transaction
across the crossbar switch, thus remaining less intrusive during a debug session.
It is important to note that these DAP control and status registers are not memory-mapped
within the system memory map, and are only accessible via the Debug Access Port using
SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers
shown in this table.
Table 9-3. MDM-AP register summary
Address Register Description
0x0100_0000 Status See MDM-AP Status Register
0x0100_0004 Control See MDM-AP Control Register
0x0100_00FC IDR Read-only identification register that
always reads as 0x001C_0020
Chapter 9 Debug
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 151