NXP Semiconductors K32 L2A Series, Reference Manual, Page: 139 / 1379

Peripheral Doze can therefore be used to disable selected bus masters or slaves for the
duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves
immediately on entry into any stop mode (or Compute Operation), instead of waiting for
the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it
can be used to disable selected bus masters or slaves that should remain inactive during a
DMA wakeup.
If the flash memory is not being accessed during WAIT and PSTOP modes, then the
Flash Doze mode can be used to reduce power consumption, at the expense of a slightly
longer wake-up when executing code and vectors from flash. It can also be used to reduce
power consumption during Compute Operation when executing code and vectors from
SRAM.
7.2.5 Clock gating
To conserve power, the clocks to most modules can be turned off using the CGC bit in
the PCC module registers. For more details, see the
Clock Distribution and PCC chapters.
7.3 Power Mode Architecture
The power mode architecture consists of a digital power domain and an analog power
domain. The device has the following external power connections.
• Digital ground (VSS)
• Digital supply (VDD)
• Analog ground (VSSA)
• Analog supply (VDDA)
The Analog to Digital converters ADC0 and Digital to Analog Converter DAC0 are
powered via a separate analog domain: VSSA and VDDA.
GPIO port pads are powered directly from VDD.
7.4 Power modes
The System Mode Controller (SMC) provides multiple power options to allow the user to
optimize power consumption for the level of functionality needed .
Chapter 7 Power Management
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 139