NXP Semiconductors K32 L2A Series, Reference Manual, Page: 130 / 1379

This device supports booting from internal flash with the reset vectors located at
addresses 0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception
vector table to RAM.
6.3.2 FOPT boot options
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains read-
only bits that are loaded from the NVM's option byte in the flash configuration field. The
default setting for all values in the FTFA_FOPT register is logic 1 since it is copied from
the option byte residing in flash, which has all bits as logic 1 in the flash erased state. To
configure for alternate settings, program the appropriate bits in the NVM option byte.
The new settings will take effect on subsequent POR, VLLSx recoveries, and any system
reset. For more details on programming the option byte, see the flash memory chapter.
The MCU uses FTFA_FOPT to configure the device at reset as shown in the following
table.
NOTE
An FTFA_FOPT value of 0x00 is invalid and will be ignored.
The FOPT register is written to 0xFF if the contents of the
Flash nonvolatile option are 0x00.
Table 6-3. Flash Option Register (FTFA_FOPT) definition
Bit
Num
Field Value Definition
7-6 BOOTSRC_SEL Boot Source Selection: these bits select the boot sources if boot pin option bit
BOOTPIN_OPT = 1
00
Boot from Flash
01 Reserved
10 Reserved
11 Boot from ROM
5 FAST_INIT Selects initialization speed on POR, VLLSx, and any system reset.
0
Slower initialization: The flash initialization will be slower with the benefit of
reduced average current during this time. The duration of the recovery will be
controlled by the clock divider selection determined by the LPBOOT setting.
1 Fast Initialization: The flash has faster recoveries at the expense of higher current
during these times.
3 RESET_PIN_CFG Enables/disables control for the RESET pin.
0
RESET_b pin is disabled following a POR and cannot be enabled as reset
function. When this option is selected, there could be a short period of contention
during a POR ramp where the device drives the pin low prior to establishing the
Table continues on the next page...
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K32 L2A Reference Manual, Rev. 2, 01/2020
130 NXP Semiconductors