NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1287 / 1379

Chapter 50
Time Stamp Timer Module (TSTMR)
50.1 Introduction
The Time Stamp Timer (TSTMR) is a 56-bit clock cycle counter, reset by system reset.
50.1.1 Features
• Free-running Time Stamp Timer
50.2 Memory map and register definition
The TSTMR module contains a 56-bit clock cycle counter, which is reset by system reset.
NOTE
The TSTMR registers can be read with 32-bit accesses only.
TSTMR memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_50F0 Time Stamp Timer Register Low (TSTMR0_L) 32 R 0000_0000h 50.2.1/1288
4007_50F4 Time Stamp Timer Register High (TSTMR0_H) 32 R 0000_0000h 50.2.2/1288
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1287