NXP Semiconductors K32 L2A Series, Reference Manual, Page: 126 / 1379

6.2.2.3 High-voltage detect (HVD)
The chip includes a system to guard against high-voltage conditions. See:
• High-voltage detect (HVD) system
• HVD reset operation
• HVD interrupt operation
6.2.2.4 Watchdog timer (WDOG)
The watchdog timer monitors the operation of the system by expecting periodic
communication from the software. This communication is generally known as servicing
(or refreshing) the watchdog. If this periodic refreshing does not occur, then the
watchdog issues a system reset, which causes RCM_SRS[WDOG] to set.
6.2.2.5 Low leakage wakeup (LLWU)
The LLWU module provides the means for a number of external pins and a number of
internal peripherals to wake the MCU from low leakage power modes. It also allows for
asynchronous DMA wakeup from LLS for certain peripherals.
The LLWU module is functional only in low leakage power modes. In VLLSx modes, all
enabled inputs to the LLWU can generate a system reset.
After a system reset, the LLWU retains the flags indicating the input source of the last
wakeup until the user clears them.
NOTE
Some flags are cleared in the LLWU and some flags are
required to be cleared in the peripheral module. Refer to the
individual peripheral chapters for more information.
6.2.2.6 Clock monitor reset sources
The SCG module contains a clock monitor with reset and interrupt request capability for
SPLL and SOSC clocks.
NOTE
To prevent unexpected reset events, all clock monitors must be
disabled before entering any low-power modes, including
VLPR and VLPW.
Reset
K32 L2A Reference Manual, Rev. 2, 01/2020
126 NXP Semiconductors