NXP Semiconductors K32 L2A Series, Reference Manual, Page: 120 / 1379

• The DIVCORE_CLK should not exceed 8MHz in Low Power RUN mode. The
DIVSLOW_CLK should not exceed 1MHz.
• Peripheral functional clocks from xxxDIV3_CLK or xxxDIV1_CLK in normal RUN
mode should be limited to 72 MHz.
• Peripheral functional clocks from xxxDIV3_CLK or xxxDIV1_CLK in high speed
RUN mode should be limited to 96MHz.
• When switching from normal RUN mode to HSRUN mode, clock sources should be
enabled prior to changing run modes. Once the Core is in HSRUN mode, if the
normal RUN mode source oscillator is not being used then it can then be disabled.
• When switching from normal RUN mode to VLPR mode, clock sources should be
enabled prior to changing run modes. Once the Core is in VLPR mode, if the normal
RUN mode source oscillator is not being used then it can then be disabled.
• When switching from VLPR mode to normal RUN mode, clock sources should be
enabled prior to changing run modes. Once the Core is in normal RUN mode, if the
VLPR mode source oscillator is not being used then it can then be disabled.
• When switching from HSRUN mode to normal RUN mode, clock sources should be
enabled prior to changing run modes. Once the Core is in normal RUN mode, if the
HSRUN mode source oscillator is not being used then it can then be disabled.
• Switching from VLPR to HSRUN mode, and vice versa is not supported. Users must
switch to normal RUN mode first then into either HSRUN or VLPR mode.
Refer to the SMC chapter for further power mode information.
5.12 Clock divider values after reset
The device resets to either normal RUN mode, or VLP Run mode and the SIRC clock
source is used to drive the DIVCORE_CLK. The specific run mode is selected via NVM
(IFR) options.
In addition to the run mode when the device resets, the DIVCORE_CLK divide ratio is
determined by the NVM (IFR) options. The IFR bits set the DIVCORE field in the
SCG’s Run Clock Control Register (SCG_RCCR). Similarly the DIVSLOW_CLK divide
ratio is also determined by the NVM (IFR) options.
Out of reset, the SIRC module is enabled and used as the main clock source out of reset.
This provides an 8MHz source clock.
The PLL, FIRC and SOSC are disabled out of reset.
All peripheral clocks xxxDIVy_CLK’s are disabled out of reset.
The speed of the DIVCORE_CLK and DIVSLOW_CLK out of reset can be modified by
programming NVM(IFR) register bits.
Clock divider values after reset
K32 L2A Reference Manual, Rev. 2, 01/2020
120 NXP Semiconductors