NXP Semiconductors K32 L2A Series, Reference Manual, Page: 118 / 1379

Table 5-2. Clock Definitions
Clock name Description
Clock name Description
SOSC System Oscillator clock from the OSC module or an external squarewave input on EXTAL
pin. One of the four clock sources. References to ERCLK are to this SOSC clock
SIRC Slow Internal RC oscillator clock (2 or 8 MHz). One of the four clock sources.
FIRC Fast Internal RC oscillator clock (48-60 MHz). One of the four clock sources.
SPLL System PLL clock, that is a multiple of the FIRC or SOSC. One of the four clock sources.
DIVCORE_CLK Main clock for CPU platform and closely tighly coupled peripherals/modules. This clock is
derived from one of the four clock sources
DIVSLOW_CLK Main clock used for peripheral/CPU interfacing and clocking the flash module. This clock is
derived from DIVCORE_CLK.
SOSCDIV1_CLK Alternative clock for clocking peripherals tightly coupled with CPU, sourced from SOSC.
Selected via PCCn register of peripheral
SIRCDIV1_CLK Alternative clock for clocking peripherals tightly coupled with CPU, sourced from SIRC.
Selected via PCCn register of peripheral
FIRCDIV1_CLK Alternative clock for peripherals tightly coupled with CPU, sourced from FIRC. Selected via
PCCn register of peripheral
SPLLDIV1_CLK Alternative clock for clocking peripherals tightly coupled with CPU, sourced from SPLL.
Selected via PCCn register of peripheral
SOSCDIV3_CLK Alternative clock for clocking low power peripherals, sourced from SOSC. Selected via PCCn
register of peripheral
SIRCDIV3_CLK Alternative clock for clocking low power peripherals, sourced from SIRC. Selected via PCCn
register of peripheral
FIRCDIV3_CLK Alternative clock for clocking low power peripherals, sourced from FIRC. Selected via PCCn
register of peripheral
SPLLDIV3_CLK Alternative clock for clocking low power peripherals, sourced from SPLL. Selected via PCCn
register of peripheral
OSC32KCLK System oscillator output clock when either a 32 kHz crystal or 32 kHz external clock source is
provide to the EXTAL pin.
LPO PMC 1kHz output. Used to clock some periodic timers when in low power stop modes to
provide periodic wake-up or periodic interrupts. The LPO is independent of the SCG and is
controlled via the PMC module.
5.10 Clocking details
The following table provide more information regarding the on-chip clocks.
Table 5-3. Detailed Clock Summary
Clock name Run mode - Clock
Frequency
VLPR mode -
Clock Frequency
HSRUN mode -
Clock Frequency
Clock source Clock can be
disabled when…
DIVCORE_CLK Up to 72 MHz Up to 8 MHz Up to 96 MHz SCG When both CPUs
are in any stop
Table continues on the next page...
Clocking details
K32 L2A Reference Manual, Rev. 2, 01/2020
118 NXP Semiconductors