NXP Semiconductors K32 L2A Series, Reference Manual, Page: 117 / 1379

• SPLL provides SPLLDIV1_CLK, SPLLDIV2_CLK and SPLLDIV3_CLK
• SOSC provides SOSCDIV1_CLK, SOSCDIV2_CLK and SOSCDIV3_CLK
• FIRC provides FIRCDIV1_CLK, FIRCDIV2_CLK and FIRCDIV3_CLK
• SIRC provides SIRCDIV1_CLK, SIRCDIV2_CLK and SIRCDIV3_CLK
NOTE
The twelve additional clock trees may not all be implemented
on every device.
Each peripheral that can support alternative clock inputs, will have it’s own dedicated
PCCn register which allows selection of one of the above 12 clock inputs. The PCCn will
also provide a clock gate enable/disable to the peripheral. The CPU will gain access to
these peripherals referencing either the DIVSLOW_CLK or DIVCORE_CLK with the
peripheral.
See SCG and PCC chapters for further details.
5.8 Other Clock Sources
5.8.1 OSC32KCLK
The SCG also provide an additional output from the SOSC, named OSC32KCLK, which
is used when the OSC is working from an external crystal of 32KHz or external 32KHz
clock. This signal is fed directly to some low power peripherals to allow slower clocking
in low power modes.
5.8.2 LPO Low Power Oscillator
The Low Power Oscillator (LPO) is an internal 1KHz RC oscillator and is not part of the
SCG. It is controlled via the PMC module. It provides an optional clock input for
peripherals that are required to operate in low power modes
5.9 Clock definitions
The following table describes the clocks in this device.
Chapter 5 Clock Distribution
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 117