NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1158 / 1379

TPMx_CONF field descriptions (continued)
Field Description
0 TPM counter continues incrementing or decrementing after overflow
1 TPM counter stops incrementing or decrementing after overflow.
16
CSOT
Counter Start on Trigger
When set, the TPM counter will not start incrementing after it is enabled until a rising edge on the selected
trigger input is detected. If the TPM counter is stopped due to an overflow, a rising edge on the selected
trigger input will also cause the TPM counter to start incrementing again.
The trigger input is ignored if the TPM counter is paused during debug mode or doze mode. This field
should only be changed when the TPM counter is disabled.
0 TPM counter starts to increment immediately, once it is enabled.
1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected,
after it has been enabled or after it has stopped due to overflow.
15–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9
GTBEEN
Global time base enable
Configures the TPM to use an externally generated global time base counter. When an externally
generated timebase is used, the internal TPM counter is not used by the channels but can be used to
generate a periodic interruptor DMA request using the Modulo register and timer overflow flag.
0 All channels use the internally generated TPM counter as their timebase
1 All channels use an externally generated global timebase as their timebase
8
GTBSYNC
Global Time Base Synchronization
When enabled, the TPM counter is synchronized to the global time base. It uses the global timebase
enable, trigger and overflow to ensure the TPM counter starts incrementing at the same time as the global
timebase, stops incrementing at the same time as the global timebase and is reset at the same time as the
global timebase. This field should only be changed when the TPM counter is disabled.
0 Global timebase synchronization disabled.
1 Global timebase synchronization enabled.
7–6
DBGMODE
Debug Mode
Configures the TPM behavior in debug mode. All other configurations are reserved.
00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture
events are also ignored.
11 TPM counter continues in debug mode.
5
DOZEEN
Doze Enable
Configures the TPM behavior in wait mode.
0 Internal TPM counter continues in Doze mode.
1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input
capture events are also ignored.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Memory Map and Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1158 NXP Semiconductors