NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1117 / 1379

SMC_STOPCTRL field descriptions (continued)
Field Description
0 POR detect circuit is enabled in VLLS0
1 POR detect circuit is disabled in VLLS0
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
LPOPO
LPO Power Option
Controls whether the 1 kHz LPO clock is enabled in LLS/VLLSx modes.
NOTE: During VLLS0 mode, the LPO clock is disabled by hardware and this bit has no effect.
0 LPO clock is enabled in LLS/VLLSx
1 LPO clock is disabled in LLS/VLLSx
LLSM LLS or VLLS Mode Control
This field controls whichLLS or VLLS sub-mode to enter if STOPM=LLSx orVLLSx.
000 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
001
VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
010
VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
011
VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
100 Reserved
101 Reserved
110 Reserved
111 Reserved
44.3.6 Power Mode Status register (SMC_PMSTAT)
PMSTAT is a read-only, one-hot register which indicates the current power mode of the
system.
NOTE
This register is reset on Chip POR not VLLS and by reset types
that trigger Chip POR not VLLS. It is unaffected by reset types
that do not trigger Chip POR not VLLS. See the Reset section
details for more information.
When in HSRUN mode, any reset causes the system to exit to normal RUN mode after
the MCU exits its reset flow. The PMSTAT field is then automatically updated to show
RUN as the current power mode.
Chapter 44 System Mode Controller (SMC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1117