NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1061 / 1379

SCG_CSR field descriptions (continued)
Field Description
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
If SPLL is selected as system clock source, the maximum DIVCORE value is Divide-by-4.
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DIVSLOW Slow Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
Chapter 42 System Clock Generator (SCG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1061