NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1031 / 1379

Table 40-3. GPIO interface-detailed signal descriptions
Signal I/O Description
and input may be asserted
asynchronously to the system
clock.
Deassertion: When output,
this signal occurs on the
rising-edge of the system
clock. For input, it may occur
at any time and input may be
asserted asynchronously to
the system clock.
NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.
40.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error.
GPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_F000 Port Data Output Register (GPIOA_PDOR) 32 R/W 0000_0000h 40.2.1/1033
4000_F004 Port Set Output Register (GPIOA_PSOR) 32
W
(always
reads 0)
0000_0000h 40.2.2/1033
4000_F008 Port Clear Output Register (GPIOA_PCOR) 32
W
(always
reads 0)
0000_0000h 40.2.3/1034
4000_F00C Port Toggle Output Register (GPIOA_PTOR) 32
W
(always
reads 0)
0000_0000h 40.2.4/1034
4000_F010 Port Data Input Register (GPIOA_PDIR) 32 R 0000_0000h 40.2.5/1035
4000_F014 Port Data Direction Register (GPIOA_PDDR) 32 R/W 0000_0000h 40.2.6/1035
4000_F040 Port Data Output Register (GPIOB_PDOR) 32 R/W 0000_0000h 40.2.1/1033
4000_F044 Port Set Output Register (GPIOB_PSOR) 32
W
(always
reads 0)
0000_0000h 40.2.2/1033
Table continues on the next page...
Chapter 40 General-Purpose Input/Output (GPIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1031